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DAC8544 Datasheet(PDF) 4 Page - Texas Instruments

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Part No. DAC8544
Description  QUAD, 16-BIT, RAIL-TO-RAIL VOLTAGE OUTPUT, PARALLEL INTERFACE, DIGITAL-TO-ANALOG CONVERTER
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

DAC8544 Datasheet(HTML) 4 Page - Texas Instruments

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TIMING CHARACTERISTICS
tW1
tW5
tW2
tsu1
th1
tsu3
th3
th4
tsu2
th2
td1
tsu4
th2
tw4
tW3
ts
±0.003% of FSR Error Bands
Data Out Valid
Data In Valid
CS
R/W
Data I/O
DB0−DB15
LDAC
V(OUT)
DAC8544
SLAS420 – MAY 2004
IOV
DD = 1.8 V to 5.5 V; VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications –40°C to 85°C (unless
otherwise noted)
MIN
TYP
MAX
UNIT
tw1
Pulse width: CS low for valid write
20
ns
tsu1
Setup time: R/W low before CS falling
0
ns
tsu2
Setup time: data in valid before CS falling
0
ns
th1
Hold time: R/W low after CS rising
10
ns
th2
Hold time: data in valid after CS rising
15
ns
tw2
Pulse width: CS low for valid read
40
ns
tsu3
Setup time: R/W high before CS falling
30
ns
td1
Delay time: data out valid after CS falling
60
80
ns
th3
Hold time: R/W high after CS rising
10
ns
th4
Hold time: data out valid after CS rising
5
20
ns
tsu4
Setup time: LDAC rising after CS falling
10
ns
td2
Delay time: CS low after LDAC rising
50
ns
tw3
Pulse width: LDAC low
40
ns
tw4
Pulse width: LDAC high
40
ns
tw5
Pulse width: CS high
80
ns
tw6
Pulse width: RST low
40
ns
tw7
Pulse width: RST high
40
ns
tS
VOUT Settling time (settling time for a full-scale code change)
10
µs
Data Read/Write Timing
4


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