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HB56SW3272ESK-5 Datasheet(PDF) 9 Page - Hitachi Semiconductor |
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HB56SW3272ESK-5 Datasheet(HTML) 9 Page - Hitachi Semiconductor |
9 / 29 page HB56SW3272ESK-5/6 9 AC Characteristics (Ta = 0 to +70 °C, V CC = 3.3 V ±0.3 V, VSS = 0 V) * 1, *2, *19 Test Conditions • Input rise and fall time: 2 ns • Input levels: V IL = 0 V, VIH = 3 V • Input timing reference levels: 0.8 V, 2.0 V • Output timing reference levels: 0.8 V, 2.0 V • Output load: 1 TTL gate + C L (100 pF) (Including scope and jig) • Ambient illuminance: Under 100 lx Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) 50 ns 60 ns Parameter Symbol Min Max Min Max Unit Notes Random read or write cycle time t RC 84 — 104 — ns RAS precharge time t RP 30 — 40 — ns CAS precharge time t CP 8 — 10 — ns RAS pulse width t RAS 50 10000 60 10000 ns CAS pulse width t CAS 8 10000 10 10000 ns Row address setup time t ASR 5— 5— ns Row address hold time t RAH 8 — 10 — ns Column address setup time t ASC 0— 0— ns Column address hold time t CAH 8 — 10 — ns RAS to CAS delay time t RCD 12 32 14 40 ns 3 RAS to column address delay time t RAD 10 20 12 25 ns 4 RAS hold time t RSH 18 — 20 — ns CAS hold time t CSH 35 — 40 — ns CAS to RAS precharge time t CRP 10 — 10 — ns OE to Din delay time t OED 18 — 20 — ns 5 OE delay time from Din t DZO 0— 0— ns 6 CAS delay time from Din t DZC 0— 0— ns 6 Transition time (rise and fall) t T 2 50 2 50 ns 7 |
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