Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

MM54HC76 Datasheet(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. MM54HC76
Description  Dual J-K Flip-Flops with Preset and Clear
Download  6 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
Logo 

MM54HC76 Datasheet(HTML) 3 Page - National Semiconductor (TI)

   
Zoom Inzoom in Zoom Outzoom out
 3 / 6 page
background image
AC Electrical Characteristics VCCe5V TAe25 C CLe15 pF tretfe6ns
Symbol
Parameter
Conditions
Typ
Guaranteed Limit
Units
fMAX
Maximum Operating Frequency
50
30
MHz
tPHL tPLH
Maximum Propagation Delay Clock to Q or Q
16
21
ns
tPHL tPLH
Maximum Propagation Delay Clear to Q or Q
21
26
ns
tPHL tPLH
Maximum Propagation Delay Preset to Q or Q
23
28
ns
tREM
Minimum Removal Time
10
20
ns
ts
Minimum Setup Time J or K to Clock
14
20
ns
tH
Minimum Hold Time J or K to Clock
b
30
ns
tW
Minimum Pulse Width Preset Clear or Clock
10
16
ns
AC Electrical Characteristics CLe50 pF tretfe6 ns (unless otherwise specified)
TAe25 C
74HC
54HC
Symbol
Parameter
Conditions
VCC
TAeb40 to 85 CTAeb55 to 125 C
Units
Typ
Guaranteed Limits
fMAX
Maximum Operating
20V
9
5
4
3
MHz
Frequency
45V
45
27
21
18
MHz
60V
53
31
24
20
MHz
tPHL tPLH
Maximum Propagation
20V
100
126
160
183
ns
Delay Clock to Q or Q
45V
20
25
31
37
ns
60V
17
21
27
32
ns
tPHL tPLH
Maximum Propagation
20V
126
155
191
250
ns
Delay Clear to Q or Q
45V
25
31
39
47
ns
60V
21
26
33
40
ns
tPHL tPLH
Maximum Propagation
20V
137
165
210
240
ns
Delay Preset to Q or Q
45V
27
33
41
50
ns
60V
23
28
35
40
ns
tREM
Minimum Removal Time
20V
55
100
125
150
ns
Preset or Clear
45V
11
20
25
30
ns
to Clock
60V
9
17
21
25
ns
ts
Minimum Setup Time
20V
77
100
125
150
ns
J or K to Clock
45V
15
20
25
30
ns
60V
13
17
21
25
ns
tH
Minimum Hold Time
20V
b
30
0
0
ns
J or K from Clock
45V
b
30
0
0
ns
60V
b
30
0
0
ns
tW
Minimum Pulse Width
20V
55
80
100
120
ns
Preset Clear or Clock
45V
11
16
20
24
ns
60V
9
14
18
21
ns
tTLH tTHL
Maximum Output Rise
20V
30
75
95
110
ns
and Fall Time
45V
8
15
19
22
ns
60V
7
13
16
19
ns
tr tf
Maximum Input Rise and
20V
1000
1000
1000
ns
Fall Time
45V
500
500
500
ns
60V
400
400
400
ns
CPD
Power Dissipation
(per flip-flop)
80
pF
Capacitance (Note 5)
CIN
Maximum Input
5
10
10
10
pF
Capacitance
Note 5
CPD determines the no load dynamic power consumption PDeCPD VCC2 faICC VCC and the no load dynamic current consumption ISeCPD VCC faICC
3


Html Pages

1  2  3  4  5  6 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn