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TUSB3410 Datasheet(PDF) 5 Page - Texas Instruments

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Part No. TUSB3410
Description  USB TO SERIAL PORT CONTROLLER
Download  92 Pages
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
Logo TI - Texas Instruments

TUSB3410 Datasheet(HTML) 5 Page - Texas Instruments

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6
DMA Controller
6–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1
DMA Controller Registers
6–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.1
DMACDR1: DMA Channel Definition Register (UART Transmit
Channel) (Addr:FFE0)
6–2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.2
DMACSR1: DMA Control And Status Register (UART Transmit
Channel) (Addr:FFE1)
6–3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.3
DMACDR3: DMA Channel Definition Register (UART Receive
Channel) (Addr:FFE4)
6–4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.4
DMACSR3: DMA Control And Status Register (UART Receive
Channel) (Addr:FFE5)
6–5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2
Bulk Data I/O Using the EDB
6–5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.1
IN Transaction (TUSB3410 to Host)
6–5
. . . . . . . . . . . . . . . . . . .
6.2.2
OUT Transaction (Host to TUSB3410)
6–6
. . . . . . . . . . . . . . . . .
7
UART
7–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1
UART Registers
7–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.1
RDR: Receiver Data Register (Addr:FFA0)
7–1
. . . . . . . . . . . . .
7.1.2
TDR: Transmitter Data Register (Addr:FFA1)
7–1
. . . . . . . . . . .
7.1.3
LCR: Line Control Register (Addr:FFA2)
7–2
. . . . . . . . . . . . . . .
7.1.4
FCRL: UART Flow Control Register (Addr:FFA3)
7–3
. . . . . . . .
7.1.5
Transmitter Flow Control
7–4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.6
MCR: Modem-Control Register (Addr:FFA4)
7–5
. . . . . . . . . . . .
7.1.7
LSR: Line-status Register (Addr:FFA5)
7–6
. . . . . . . . . . . . . . . .
7.1.8
MSR: Modem-Status Register (Addr:FFA6)
7–7
. . . . . . . . . . . .
7.1.9
DLL: Divisor Register Low Byte (Addr:FFA7)
7–8
. . . . . . . . . . .
7.1.10
DLH: Divisor Register High Byte (Addr:FFA8)
7–8
. . . . . . . . . . .
7.1.11
Baud-rate Calculation
7–8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.12
XON: Xon Register (Addr:FFA9)
7–9
. . . . . . . . . . . . . . . . . . . . . .
7.1.13
XOFF: Xoff Register (Addr:FFAA)
7–9
. . . . . . . . . . . . . . . . . . . . .
7.1.14
MASK: UART Interrupt-Mask Register (Addr:FFAB)
7–10
. . . . .
7.2
UART Data Transfer
7–10
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.1
Receiver Data Flow
7–10
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.2
Hardware Flow Control
7–11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.3
Auto RTS (Receiver Control)
7–11
. . . . . . . . . . . . . . . . . . . . . . . . .
7.2.4
Auto CTS (Transmitter Control)
7–11
. . . . . . . . . . . . . . . . . . . . . . .
7.2.5
Xon/Xoff Receiver Flow Control
7–12
. . . . . . . . . . . . . . . . . . . . . . .
7.2.6
Xon/Xoff Transmit Flow Control
7–12
. . . . . . . . . . . . . . . . . . . . . . .
8
Expanded GPIO Port
8–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1
Input/Output and Control Registers
8–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1.1
PUR_3: GPIO Pullup Register For Port 3 (Addr:FF9E)
8–1
. . .
9
Interrupts
9–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.1
8052 Interrupt and Status Registers
9–1
. . . . . . . . . . . . . . . . . . . . . . . . . . .
9.1.1
8052 Standard Interrupt Enable (SIE) Register
9–1
. . . . . . . . .
9.1.2
Additional Interrupt Sources
9–1
. . . . . . . . . . . . . . . . . . . . . . . . . .
9.1.3
VECINT: Vector Interrupt Register (Addr:FF92)
9–2
. . . . . . . . .
9.1.4
Logical Interrupt Connection Diagram (Internal/External)
9–3
.


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