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COP8CCE9HLQ7 Datasheet(PDF) 9 Page - National Semiconductor (TI) |
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COP8CCE9HLQ7 Datasheet(HTML) 9 Page - National Semiconductor (TI) |
9 / 75 page AC Electrical Characteristics (0˚C ≤ T A ≤ +70˚C) (Continued) Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Parameter Conditions Min Typ Max Units Input Pulse Width Interrupt Input High Time 1 t C Interrupt Input Low Time 1 t C Timer 1 Input High Time 1 t C Timer 1 Input Low Time 1 t C Timer 2 Input High Time (Note 6) 1 MCLK or t C Timer 2 Input Low Time (Note 6) 1 MCLK or t C Output Pulse Width Timer 2 Output High Time 150 ns Timer 2 Output Low Time 150 ns USART Bit Time when using External CKX 6 CKI periods USART CKX Frequency when being Driven by Internal Baud Rate Generator 2 MHz Reset Pulse Width 1 t C tC = instruction cycle time. Note 2: Maximum rate of voltage change must be < 0.5 V/ms. Note 3: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to VCC and outputs driven low but not connected to a load. Note 4: The HALT mode will stop CKI from oscillating. Measurement of IDD HALT is done with device neither sourcing nor sinking current; with A. B, G0, G2–G5, H and L programmed as low outputs and not driving a load; all inputs tied to VCC; A/D converter and clock monitor and BOR disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register. Note 5: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages > VCC and the pins will have sink current to VCC when biased at voltages > VCC (the pins do not have source current when biased at a voltage below VCC). These two pins will not latch up. The voltage at the pins must be limited to < 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes ESD transients. Note 6: If timer is in high speed mode, the minimum time is 1 MCLK. If timer is not in high speed mode, the minimum time is 1 tC. Note 7: Absolute Maximum Ratings should not be exceeded. Note 8: Vcc must be valid and stable before G6 is raised to a high voltage. A/D Converter Electrical Characteristics (0˚C ≤ T A ≤ +70˚C) (Single-ended mode only) Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Parameter Conditions Min Typ Max Units Resolution 10 Bits DNL V CC =5V ±1 LSB DNL V CC =3V ±1 LSB INL V CC =5V ±2 LSB INL V CC =3V ±4 LSB Offset Error V CC =5V ±1.5 LSB Offset Error V CC =3V ±2.5 LSB Gain Error V CC =5V ±1.5 LSB Gain Error V CC =3V ±2.5 LSB Input Voltage Range 2.7V ≤ V CC < 5.5V 0 V CC V Analog Input Leakage Current 0.5 µA Analog Input Resistance (Note 9) 6k Ω Analog Input Capacitance 7pF Conversion Clock Period 4.5V ≤ V CC < 5.5V 2.7V ≤ V CC < 4.5V 0.8 1.2 30 30 µs µs Conversion Time (including S/H Time) 15 A/D Conversion Clock Cycles Operating Current on AV CC AV CC = 5.5V 0.2 0.6 mA Note 9: Resistance between the device input and the internal sample and hold capacitance. www.national.com 9 |
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