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TLC2262CD Datasheet(PDF) 47 Page - Texas Instruments |
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TLC2262CD Datasheet(HTML) 47 Page - Texas Instruments |
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47 / 59 page  TLC226x, TLC226xA Advanced LinCMOS RAIL-TO-RAIL OPERATIONAL AMPLIFIERS SLOS177D – FEBRUARY 1997 – REVISED MARCH 2001 47 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION driving large capacitive loads The TLC226x is designed to drive larger capacitive loads than most CMOS operational amplifiers. Figure 58 and Figure 59 illustrate its ability to drive loads greater than 400 pF while maintaining good gain and phase margins (Rnull = 0). A smaller series resistor (Rnull) at the output of the device (see Figure 62) improves the gain and phase margins when driving large capacitive loads. Figure 58 and Figure 59 show the effects of adding series resistances of 10 Ω, 20 Ω, 50 Ω, and 100 Ω. The addition of this series resistor has two effects: the first is that it adds a zero to the transfer function and the second is that it reduces the frequency of the pole associated with the output load in the transfer function. The zero introduced to the transfer function is equal to the series resistance times the load capacitance. To calculate the improvement in phase margin, equation 1 can be used. ∆Θ m1 + tan –1 2 × π× UGBW × R null × C L Where : (1) ∆Θ m1 + improvement in phase margin UGBW + unity-gainbandwidthfrequency R null + output series resistance C L + load capacitance The unity-gain bandwidth (UGBW) frequency decreases as the capacitive load increases (see Figure 60). To use equation 1, UGBW must be approximated from Figure 60. Using equation 1 alone overestimates the improvement in phase margin, as illustrated in Figure 61. The overestimation is caused by the decrease in the frequency of the pole associated with the load, thus providing additional phase shift and reducing the overall improvement in phase margin. The pole associated with the load is reduced by the factor calculated in equation 2. F + 1 1 ) gm × R null Where : (2) F + factor reducingfrequencyof pole gm + small-signaloutput transconductance (typically 4.83 × 10 – 3 mhos) R null + output series resistance For the TLC226x, the pole associated with the load is typically 7 MHz with 100-pF load capacitance. This value varies inversely with CL: at CL = 10 pF, use 70 MHz, at CL = 1000 pF, use 700 kHz, and so on. Reducing the pole associated with the load introduces phase shift, thereby reducing phase margin. This results in an error in the increase in phase margin expected by considering the zero alone (equation 1). Equation 3 approximates the reduction in phase margin due to the movement of the pole associated with the load. The result of this equation can be subtracted from the result of the equation in equation 1 to better approximate the improvement in phase margin. |
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