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TDA8029 Datasheet(PDF) 8 Page - NXP Semiconductors |
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TDA8029 Datasheet(HTML) 8 Page - NXP Semiconductors |
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8 / 58 page  2003 Oct 30 8 Philips Semiconductors Product specification Low power single card reader TDA8029 Additional features of the controller are: • 80C51 central processing unit • Full static operation • Security bits: ROM 2 bits • Encryption array of 64 bits • 4-level priority structure • 6 interrupt sources • Full-duplex enhanced UART with framing error detection and automatic address recognition • Power control modes; clock can be stopped and resumed, Idle mode and Power-down mode • Wake-up from Power-down by falling edge on INT0_N, INT1_N and RX with an embedded delay counter • Programmable clock out • Second DPTR register • Asynchronous port reset • Low EMI by inhibit ALE. Table 1 gives a list of main features to get a better understanding of the differences between a standard 80C51, an 8XC51FB and the embedded controller in the TDA8029. Table 2 shows an overview of the special function registers. Table 1 Principal blocks in 80C51, 8XC51FB and TDA8029 FEATURE 80C51 8XC51FB TDA8029 ROM 4 kbytes 16 kbytes 16 kbytes RAM 128 bytes 256 bytes 256 bytes ERAM (MOVX) no 256 bytes 512 bytes PCA no yes no WDT no yes no T0 yes yes yes T1 yes yes yes T2 no yes yes lowest interrupt priority-vector 002Bh lowest interrupt priority-vector 002Bh 4-level priority interrupt no yes yes enhanced UART no yes yes delay counter no no yes |
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Similar Description - TDA8029 |
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