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http://www.union-ic.com Rev.01 Jan.2015

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UM805/811/812

Detailed Description

RESET Timing

The reset signal is asserted LOW for the UM811 and HIGH for the UM812 when the power supply

voltage falls below the threshold trip voltage and remains asserted for at least 140ms after the power

supply voltage has risen above the threshold.

RESET

RESET

5V

0V

5V

0V

5V

0V

The reset signal is asserted LOW for the UM811 and HIGH for the UM812 when MR

_______

is low and

remains asserted for at least 140ms after MR

_______

is high.

MR

RESET

RESET

HIGH

LOW

0V

0V

Figure 2. RESET vs. MR

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Timing Diagram

Reset Output

A microprocessor’s (µP’s) reset input starts the µP in a known state. These μP supervisory circuits

assert reset to prevent code execution errors during power-up, power-down, or brownout conditions.

RESET

_____________

internal timer keeps RESET

_____________

low for the reset timeout period; after this interval, RESET

_____________

goes