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PCI9080 Datasheet(PDF) 4 Page - List of Unclassifed Manufacturers

Part No. PCI9080
Description  12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS
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Maker  ETC [List of Unclassifed Manufacturers]
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PCI9080 Datasheet(HTML) 4 Page - List of Unclassifed Manufacturers

 
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PCI 9080
TABLE OF CONTENTS
©PLX Technology, Inc., 1997
Page v
Version 1.01
3.6.2.3
Deadlock and BREQo................................................................................................................................................... 26
3.6.2.3.1
Backoff.................................................................................................................................................................... 26
3.6.2.3.2
Software/Hardware Solution for Systems without Backoff Capability ..................................................................... 27
3.6.2.3.3
Software Solutions to Deadlock .............................................................................................................................. 27
3.6.2.4
Direct Slave Lock.......................................................................................................................................................... 27
3.6.3
Direct Slave Priority .......................................................................................................................................................... 27
3.7
DMA OPERATION ..................................................................................................................................................28
3.7.1
Non-Chaining Mode DMA ................................................................................................................................................. 28
3.7.2
Chaining Mode DMA......................................................................................................................................................... 29
3.7.3
DMA Data Transfers ......................................................................................................................................................... 31
3.7.3.1
Local to PCI Bus DMA Transfer.................................................................................................................................... 31
3.7.3.2
PCI to Local Bus DMA Transfer.................................................................................................................................... 32
3.7.3.3
Unaligned Transfers ..................................................................................................................................................... 32
3.7.4
Demand Mode DMA ......................................................................................................................................................... 32
3.7.5
DMA Priority...................................................................................................................................................................... 33
3.7.6
DMA Arbitration ................................................................................................................................................................ 33
3.7.6.1
End of Transfer (EOT0# or EOT1#) Input ..................................................................................................................... 33
3.7.6.2
DMA Abort .................................................................................................................................................................... 33
3.7.6.3
Local Latency and Pause Timers.................................................................................................................................. 33
3.8
VENDOR AND DEVICE ID REGISTERS ...............................................................................................................34
3.9
DOORBELL REGISTERS .......................................................................................................................................34
3.10
MAILBOX REGISTERS...........................................................................................................................................34
3.11
USER INPUT AND OUTPUT ..................................................................................................................................34
3.12
INTERRUPTS .........................................................................................................................................................35
3.12.1
PCI Interrupts (INTA#) ...................................................................................................................................................... 35
3.12.1.1
Local Interrupt Input .................................................................................................................................................. 35
3.12.1.2
Master/Target Abort Interrupt.................................................................................................................................... 35
3.12.2
Local Interrupts (LINTo#) .................................................................................................................................................. 36
3.12.2.1
Local to PCI Doorbell Interrupt.................................................................................................................................. 36
3.12.2.2
PCI to Local Doorbell Interrupt.................................................................................................................................. 36
3.12.2.3
Built-In Self Test Interrupt (BIST) .............................................................................................................................. 36
3.12.2.4
DMA Channel 0/1 Interrupts ..................................................................................................................................... 36
3.12.3
PCI SERR# (PCI NMI) ...................................................................................................................................................... 37
3.12.4
Local LSERR# (Local NMI)............................................................................................................................................... 37
3.13
I20 COMPATIBLE MESSAGE UNIT .......................................................................................................................37
3.13.1
Inbound Messages ........................................................................................................................................................... 38
3.13.2
Outbound Messages......................................................................................................................................................... 38
3.13.3
I2O Pointer Management .................................................................................................................................................. 38
3.13.4
Inbound Free List FIFO..................................................................................................................................................... 39


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