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S6J3320 Datasheet(PDF) 11 Page - Cypress Semiconductor |
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S6J3320 Datasheet(HTML) 11 Page - Cypress Semiconductor |
11 / 247 page Document Number: 002-10635 Rev.** Page 11 of 247 S6J3310/20/30/40 Series PRELIMINARY Feature Description Standby mode See the TraveoTM Platform hardware manual in detail. Standby mode with 5V (or 3V) single external power supply is available. Turning off the 1.2V external power supply in standby mode is available. The long term pulse of the indicator PWM can be outputted during RTC Standby mode. PLL / SSCG PLL See the TraveoTM Platform hardware manual in detail. Use case assumption is following. PLL − Sound system clock − Sound frequency master clock − Peripherals − Display clock − Trace clock SSCG − CPU core − GDC core − Hyper BUS − DDR-HSSPI Down spread mode is only supported and available. External Interrupts See the TraveoTM Platform hardware manual in detail. NMI See the TraveoTM Platform hardware manual in detail. 1 NMI pin. Memory Protection MPU16 AHB: See the TraveoTM Platform hardware manual in detail. MPU for AXI: ch.0 MPU for AHB: ch.1 Additional MPU for Graphic sub system, MediaLB and Ethernet AVB. They are described on the chapter of MPU for AHB and MPU for AXI To configure Lock or Unlock for both MPUXn_UNLOCK and MPUHn_UNLOCK, − Lock: 0x112ABB56 − Unlock: 0xACCABB56 Peripheral Protection See the TraveoTM Platform hardware manual in detail. Protected peripherals are described in the base address map. Internal Memories System SRAM 384kByte 1 wait cycle is necessary for RAM read at over 120MHz. Internal Memories TCRAM 128kByte Internal Memories Backup RAM 32kByte Backup RAM can only be operated in RUN mode (normal operation mode). In other mode the memory content should be retained, but it cannot be operated. SLEEP control for Backup RAM is not supported and cannot be used. |
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Similar Description - S6J3320 |
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