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BCM88335 Datasheet(PDF) 57 Page - Cypress Semiconductor |
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BCM88335 Datasheet(HTML) 57 Page - Cypress Semiconductor |
57 / 140 page WLAN Host Interfaces BCM88335 Data Sheet BROADCOM CONFIDENTIAL Broadcom® September 23, 2015 • 88335-DS100-R Page 56 Section 9: WLAN Host Interfaces SDIO v3.0 The BCM88335 WLAN section supports SDIO version 3.0, including the new UHS-I modes: • DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3V signaling). • HS: High speed up to 50 MHz (3.3V signaling). • SDR12: SDR up to 25 MHz (1.8V signaling). • SDR25: SDR up to 50 MHz (1.8V signaling). • SDR50: SDR up to 100 MHz (1.8V signaling). • SDR104: SDR up to 208 MHz (1.8V signaling). • DDR50: DDR up to 50 MHz (1.8V signaling). The SDIO interface also has the ability to map the interrupt signal on to a GPIO pin for applications requiring an interrupt different from the one provided by the SDIO interface. The ability to force control of the gated clocks from within the device is also provided. SDIO mode is enabled by strapping options. Refer to Table 16 WLAN GPIO Functions and Strapping Options. The following three functions are supported: • Function 0 Standard SDIO function (Max. BlockSize/ByteCount = 32B) • Function 1 Backplane Function to access the internal system-on-chip (SoC) address space (Max. BlockSize/ByteCount = 64B) • Function 2 WLAN Function for efficient WLAN packet transfer through DMA (Max. BlockSize/ByteCount = 512B) SDIO Pins Note: The BCM88335 is backward compatible with SDIO v2.0 host interfaces. Table 12: SDIO Pin Description SD 4-Bit Mode SD 1-Bit Mode gSPI Mode DATA0 Data line 0 DATA Data line DO Data output DATA1 Data line 1 or Interrupt IRQ Interrupt IRQ Interrupt DATA2 Data line 2 or Read Wait RW Read Wait NC Not used DATA3 Data line 3 N/C Not used CS Card select CLK Clock CLK Clock SCLK Clock CMD Command line CMD Command line DI Data input |
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