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COP988GD Datasheet(PDF) 8 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # COP988GD
Description  8-Bit CMOS ROM Based Microcontrollers with 16k
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

COP988GD Datasheet(HTML) 8 Page - National Semiconductor (TI)

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DC Electrical Characteristics (Continued)
−40˚C
≤ T
A ≤ +85˚C unless otherwise specified
Parameter
Conditions
Min
Typ
Max
Units
All others
3mA
Maximum Input Current
Room Temp
±100
mA
without Latchup (Note 7) (Note 9)
RAM Retention Voltage, V
r
500 ns Rise
2
V
and Fall Time (min)
Input Capacitance
7pF
Load Capacitance on D2
1000
pF
AC Electrical Characteristics
−40˚C
≤ T
A ≤ +85˚C unless otherwise specified
Parameter
Conditions
Min
Typ
Max
Units
Instruction Cycle Time (t
c)
Crystal, Resonator,
4.5V
≤ V
CC ≤ 5.5V
1.0
DC
µs
R/C Oscillator
4.5V
≤ V
CC ≤ 5.5V
3.0
DC
µs
CKI Clock Duty Cycle (Note 9)
f
r = Max
40
60
Rise Time (Note 9)
f
r = 10 MHz Ext Clock
5
ns
Fall Time (Note 9)
f
r = 10 MHz Ext Clock
5
ns
Inputs
t
SETUP
4.5V
≤ V
CC ≤ 5.5V
200
ns
t
HOLD
4.5V
≤ V
CC ≤ 5.5V
60
ns
Output Propagation Delay (Note 8)
R
L = 2.2k, CL = 100 pF
t
PD1,tPD0
SO, SK
4.5V
≤ V
CC ≤ 5.5V
0.7
µs
All Others
4.5V
≤ V
CC ≤ 5.5V
1.0
µs
MICROWIRE Setup Time (t
UWS) (Note 9)
20
ns
MICROWIRE Hold Time (t
UWH) (Note 9)
56
ns
MICROWIRE Output Propagation Delay
(t
UPD)
220
ns
Input Pulse Width (Note 9)
Interrupt Input High Time
1.0
t
c
Interrupt Input Low Time
1.0
t
c
Timer 1, 2, 3 Input High Time
1.0
t
c
Timer 1, 2, 3 Input Low Time
1.0
t
c
Reset Pulse Width
1.0
µs
Note 19: tc = Instruction Cycle Time
Note 20: Maximum rate of voltage change must be < 0.5 V/ms.
Note 21: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to VCC
and outputs driven low but not connected to a load.
Note 22: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations by bringing CKI high. Measurement of IDD HALT is done with device
neither sourcing nor sinking current; with L, C, G0, and G2–G5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load;
all inputs tied to VCC; clock monitor and comparator disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register. Part will pull up
CKI during HALT in crystal clock mode.
Note 23: The user must guarantee that D2 pin does not source more than 10 mA during RESET. If D2 sources more than 10 mA during reset, the device will go into
programming mode.
Note 24: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages VCC and the pins will have sink current to VCC when
biased at voltages VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750Ω (typical). These two pins
will not latch up. The voltage at the pins must be limited to < 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes ESD
transients.
Note 25: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 26: Parameter characterized but not tested.
www.national.com
8


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