ISP1160 datasheet(11/88 Pages) PHILIPS

Part #	ISP1160

Description	Embedded Universal Serial Bus Host Controller

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Manufacturer	PHILIPS [NXP Semiconductors]

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Philips Semiconductors

ISP1160

Embedded USB Host Controller

Product data

Rev. 04 — 04 July 2003

11 of 88

9397 750 11371

Most of the ISP1160’s internal control registers are 16-bit wide. Some of the internal

control registers, however, are 32-bit wide. Figure 7 shows how the ISP1160’s 32-bit

internal control register is accessed. The complete cycle of accessing a 32-bit

register consists of a command phase followed by two data phases. In the two data

phases, the microprocessor ﬁrst reads or writes the lower 16-bit data, followed by the

upper 16-bit data.

To further describe the complete access cycles of the internal control registers, the

status of some pins of the microprocessor bus interface are shown in Figure 8.

8.4 FIFO buffer RAM access by PIO mode

Since the ISP1160’s internal memory is structured as a FIFO buffer RAM, the FIFO

buffer RAM is mapped to dedicated register ﬁelds. Therefore, accessing the internal

FIFO buffer RAM is similar to accessing the internal control registers in multiple data

phases.

Fig 6.

16-bit register access cycle.

Fig 7.

32-bit register access cycle.

Fig 8.

Accessing HC control registers.

MGT937

read/write data

(16 bits)

16-bit register access cycle

t

write command

(16 bits)

MGT938

read/write data

(lower 16 bits)

32-bit register access cycle

t

read/write data

(upper 16 bits)

write command

(16 bits)

Signals

Valid status

CS_N

0

A0

1

Valid status

0

Valid status

0

RD_N,

WR_N

RD_N = 1,

WR_N = 0

RD_N = 0 (read) or

WR_N = 0 (write)

data bus

Command code

Register data

(upper word)

Register data

(lower word)

RD_N = 0 (read) or

WR_N = 0 (write)

004aaa370

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