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COP888CF Datasheet(PDF) 33 Page - National Semiconductor (TI) |
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COP888CF Datasheet(HTML) 33 Page - National Semiconductor (TI) |
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33 / 44 page  MICROWIRE/PLUS (Continued) MICROWIRE/PLUS Slave Mode Operation In the MICROWIRE/PLUS Slave mode of operation the SK clock is generated by an external source. Setting the MSEL bit in the CNTRL register enables the SO and SK functions onto the G Port. The SK pin must be selected as an input and the SO pin is selected as an output pin by setting and re- setting the appropriate bit in the Port G configuration regis- ter. Table 8 summarizes the settings required to enter the Slave mode of operation. TABLE 8. MICROWIRE/PLUS Mode Settings This table assumes that the control flag MSEL is set. G4 (SO) G5 (SK) G4 G5 Operation Config. Bit Config. Bit Fun. Fun. 1 1 SO Int. MICROWIRE/PLUS SK Master 0 1 TRI- Int. MICROWIRE/PLUS STATE SK Master 1 0 SO Ext. MICROWIRE/PLUS SK Slave 0 0 TRI- Ext. MICROWIRE/PLUS STATE SK Slave The user must set the BUSY flag immediately upon entering the Slave mode. This will ensure that all data bits sent by the Master will be shifted properly. After eight clock pulses the BUSY flag will be cleared and the sequence may be re- peated. Alternate SK Phase Operation The device allows either the normal SK clock or an alternate phase SK clock to shift data in and out of the SIO register. In both the modes the SK is normally low. In the normal mode data is shifted in on the rising edge of the SK clock and the data is shifted out on the falling edge of the SK clock. The SIO register is shifted on each falling edge of the SK clock in the normal mode. In the alternate SK phase mode the SIO register is shifted on the rising edge of the SK clock. A control flag, SKSEL, allows either the normal SK clock or the alternate SK clock to be selected. Resetting SKSEL causes the MICROWIRE/PLUS logic to be clocked from the normal SK signal. Setting the SKSEL flag selects the alter- nate SK clock. The SKSEL is mapped into the G6 configura- tion bit. The SKSEL flag will power up in the reset condition, selecting the normal SK signal. Memory Map All RAM, ports and registers (except A and PC) are mapped into data memory address space Address Contents 00 to 6F On-Chip RAM bytes 70 to BF Unused RAM Address Space C0 Timer T2 Lower Byte C1 Timer T2 Upper Byte C2 Timer T2 Autoload Register T2RA Lower Byte C3 Timer T2 Autoload Register T2RA Upper Byte C4 Timer T2 Autoload Register T2RB Lower Byte C5 Timer T2 Autoload Register T2RB Upper Byte C6 Timer T2 Control Register C7 WATCHDOG Service Register (Reg:WDSVR) C8 MIWU Edge Select Register (Reg:WKEDG) C9 MIWU Enable Register (Reg:WKEN) CA MIWU Pending Register (Reg:WKPND) CB A/D Converter Control Register (Reg:ENAD) CC A/D Converter Result Register (Reg: ADRSLT) CD to CF Reserved D0 Port L Data Register D1 Port L Configuration Register D2 Port L Input Pins (Read Only) D3 Reserved for Port L D4 Port G Data Register D5 Port G Configuration Register D6 Port G Input Pins (Read Only) D7 Port I Input Pins (Read Only) D8 Port C Data Register D9 Port C Configuration Register DA Port C Input Pins (Read Only) DB Reserved for Port C DC Port D Data Register DD to DF Reserved for Port D E0 to E5 Reserved E6 Timer T1 Autoload Register T1RB Lower Byte E7 Timer T1 Autoload Register T1RB Upper Byte E8 ICNTRL Register E9 MICROWIRE Shift Register EA Timer T1 Lower Byte EB Timer T1 Upper Byte EC Timer T1 Autoload Register T1RA Lower Byte ED Timer T1 Autoload Register T1RA Upper Byte EE CNTRL Control Register EF PSW Register F0 to FB On-Chip RAM Mapped as Registers FC X Register FD SP Register FE B Register FF Reserved Note: Reading memory locations 70-7F Hex will return all ones. Reading other unused memory locations will return undefined data. www.national.com 33 |
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