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DIR1703 Datasheet(PDF) 10 Page - Burr-Brown (TI)

[Old version datasheet] Texas Instruments acquired Burr-Brown Corporation.
Part # DIR1703
Description  DIGITAL AUDIO INTERFACE RECEIVER
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Manufacturer  BURR-BROWN [Burr-Brown (TI)]
Direct Link  http://www.burr-brown.com
Logo BURR-BROWN - Burr-Brown (TI)

DIR1703 Datasheet(HTML) 10 Page - Burr-Brown (TI)

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DIR1703
SLES007– JULY 2001
10
www.ti.com
bit rate detection
By using the SpAct frequency estimator (not the S/PDIF channel status bit), the DIR1703 automatically detects
the sample rate of an incoming S/PDIF signal and indicates the frequency at the BRATE pins.
Table 6 lists the frequency ranges reported. Except for 88.2 and 96 kHz, these sample rates are the same as
the channel status bit defined in the S/PDIF specifications. When the bit-rate is 88.2 or 96 kHz the indicator
shows the same HL value. This state is not defined in the S/PDIF specifications.
Table 6. Incoming Sample Frequency Bits
SAMPLING RATE
BRATE1
BRATE0
32 kHz
HIGH
HIGH
44.1 kHz
LOW
LOW
48 kHz
LOW
HIGH
88.2 kHz
HIGH
LOW
96 kHz
HIGH
LOW
timing specification for PLL operation
lock-up time
Lock
L
H
tINT< 1 ms
Unlock
DIN Start
PLL
Condition
PLL Status
Indicator Pin
Site UNLOCK
Figure 3. PLL Lock Up Timing
relation between audio-data-output timing and PLL condition indicator timing
In the PLL clock operation mode, when the S/PDIF signal is not detected after reset removal, audio clocks
(SCKO, BCKO, LRCKO) which are not related to S/PDIF signal are generated by SpAct. The bit rate can be
selected by setting pin BRSEL. If BRSEL is OPEN or connected to DGND, the default bit rate frequency is set
to 48 kHz. If BRSEL is connected to one of the output pins BFRAME, EMFLG, URBIT, or CSBIT, the frequency
is set to 32, 44.1, 88.2, or 96 kHz, respectively. Therefore, the initial frequency is the same as the crystal
resonator, however, its error frequency is below 1% after reset.
When the analog PLL is still unlocked after at least ten rising-edges of the S/PDIF, a S/PDIF decoder can detect
the incoming S/PDIF signal. Thus, DOUT becomes low (MUTE) until the analog PLL locks. This MUTE period
is less than 1 ms (analog PLL’s lock-up time is less than 0.5 ms). When the decoder does not detect an incoming
S/PDIF signal, UNLOCK will output high level status at the LRCKO clock transition. SCKO keeps its frequency
at the latest tracked bit rate.


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