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COP87L84FH Datasheet(PDF) 8 Page - National Semiconductor (TI) |
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COP87L84FH Datasheet(HTML) 8 Page - National Semiconductor (TI) |
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8 / 45 page  Pin Descriptions V CC and GND are the power supply pins. All VCC and GND pins must be connected. CKI is the clock input. This can come from an R/C generated oscillator, or a crystal oscillator (in conjunction with CKO). See Oscillator Description section. RESET is the master reset input. See Reset Description sec- tion. The device contains three bidirectional 8-bit I/O ports (C, G and L), where each individual bit may be independently con- figured as an input (Schmitt trigger inputs on ports L and G), output or TRI-STATE under program control. Three data memory address locations are allocated for each of these I/O ports. Each I/O port has two associated 8-bit memory mapped registers, the CONFIGURATION register and the output DATA register. A memory mapped address is also re- served for the input pins of each I/O port. (See the memory map for the various addresses associated with the I/O ports.) Figure 4 shows the I/O port configurations. The DATA and CONFIGURATION registers allow for each port bit to be in- dividually configured under software control as shown below: CONFIGURA- TION DATA Register Port Set-Up Register 0 0 Hi-Z Input (TRI-STATE Output) 0 1 Input with Weak Pull-Up 1 0 Push-Pull Zero Output 1 1 Push-Pull One Output PORT L is an 8-bit I/O port. All L-pins have Schmitt triggers on the inputs. The Port L supports Multi-Input Wake Up on all eight pins. L1 is used for the USART external clock. L2 and L3 are used for the USART transmit and receive. L4 and L5 are used for the timer input functions T2A and T2B. L6 and L7 are used for the timer input functions T3A and T3B. The Port L has the following alternate features: L7 MIWU or T3B L6 MIWU or T3A L5 MIWU or T2B L4 MIWU or T2A L3 MIWU or RDX L2 MIWU or TDX L1 MIWU or CKX L0 MIWU Port G is an 8-bit port with 5 I/O pins (G0, G2–G5), an input pin (G6), and two dedicated output pins (G1 and G7). Pins G0 and G2–G6 all have Schmitt Triggers on their inputs. Pin G1 serves as the dedicated WDOUT WATCHDOG output, while pin G7 is either input or output depending on the oscil- lator mask option selected. With the crystal oscillator option selected, G7 serves as the dedicated output pin for the CKO clock output. With the single-pin R/C oscillator mask option selected, G7 serves as a general purpose input pin but is also used to bring the device out of HALT mode with a low to high transition on G7. There are two registers associated with the G Port, a data register and a configuration register. Therefore, each of the 5 I/O bits (G0, G2–G5) can be indi- vidually configured under software control. Since G6 is an input only pin and G7 is the dedicated CKO clock output pin (crystal clock option) or general purpose in- put (R/C clock option), the associated bits in the data and configuration registers for G6 and G7 are used for special purpose functions as outlined below. Reading the G6 and G7 data bits will return zeros. Note that the chip will be placed in the HALT mode by writing a “1” to bit 7 of the Port G Data Register. Similarly the chip will be placed in the IDLE mode by writing a “1” to bit 6 of the Port G Data Register. Writing a “1” to bit 6 of the Port G Configuration Register en- ables the MICROWIRE/PLUS to operate with the alternate phase of the SK clock. The G7 configuration bit, if set high, enables the clock start up delay after HALT when the R/C clock configuration is used. Config Reg. Data Reg. G7 CLKDLY HALT G6 Alternate SK IDLE Port G has the following alternate features: G6 SI (MICROWIRE™ Serial Data Input) G5 SK (MICROWIRE Serial Clock) G4 SO (MICROWIRE Serial Data Output) G3 T1A (Timer T1 I/O) G2 T1B (Timer T1 Capture Input) G0 INTR (External Interrupt Input) Port G has the following dedicated functions: G7 CKO Oscillator dedicated output or general purpose input G1 WDOUT WATCHDOG and/or Clock Monitor dedi- cated output Port C is an 8-bit I/O port. The 40-pin device does not have a full complement of Port C pins. The unavailable pins are not terminated. A read operation for these unterminated pins will return unpredicatable values. PORT I is an eight-bit Hi-Z input port. The 28-pin device does not have a full complement of Port I pins. The unavailable pins are not terminated i.e., they are floating. A read opera- tion for these unterminated pins will return unpredictable val- ues. The user must ensure that the software takes this into account by either masking or restricting the accesses to bit operations. The unterminated Port I pins will draw power only when addressed. Port I1–I3 are used for Comparator 1. Port I4–I6 are used for Comparator 2. DS101135-6 FIGURE 4. I/O Port Configurations www.national.com 8 |
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