Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

ADS7864YB Datasheet(PDF) 10 Page - Burr-Brown (TI)

[Old version datasheet] Texas Instruments acquired Burr-Brown Corporation.
Part No. ADS7864YB
Description  500kHz, 12-Bit, 6-Channel Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER
Download  16 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  BURR-BROWN [Burr-Brown (TI)]
Homepage  http://www.burr-brown.com
Logo 

ADS7864YB Datasheet(HTML) 10 Page - Burr-Brown (TI)

Zoom Inzoom in Zoom Outzoom out
 10 / 16 page
background image
10
ADS7864
®
THEORY OF OPERATION
The ADS7864 contains two 12-bit A/D converters that operate
simultaneously. The three hold signals (HOLDA, HOLDB,
HOLDC) select the input MUX and initiate the conversion. A
simultaneous hold on all six channels can occur with all three
hold signals strobed together. The converted values are saved
in 6 registers. For each read operation the ADS7864 outputs
16 bits of information (12 Data, 3 Channel Address and Data
Valid). The Address/Mode signals (A0, A1, A2) select how
the data is read from the ADS7864. These Address/Mode
signals can define a selection of a single channel, a cycle mode
that cycles through all channels or a FIFO mode that se-
quences the data determined by the order of the Hold signals.
The FIFO mode will allow the 6 registers to be used by a
single channel pair and therefore three locations for CH X0
and three locations for CH X1 can be acquired before they are
read from the part.
EXPLANATION OF CLOCK, RESET
AND BUSY PINS
CLOCK—An external clock has to be provided for the
ADS7864. The maximum clock frequency is 8MHz. The
minimum clock cycle is 125ns (Figure 8, t 5 ), and the clock
has to remain HIGH (Figure 8, t 6) or LOW (Figure 8, t7) for
at least 40ns.
RESET—Bringing reset LOW will reset the ADS7864. It
will clear all the output registers, stop any actual conversions
and will close the sampling switches. Reset has to stay LOW
for at least 20ns (Figure 8, t8). The reset should be back
HIGH for at least 20ns (Figure 8, t9), before starting the next
conversion (negative hold edge).
BUSY—Busy goes LOW when the internal A/D converters
start a new conversion. It stays LOW as long as the conver-
sion is in progress (Figure 9, 13 clock-cycles, t10) and rises
again, after the data is latched to the output register. With
busy going high, the new data can be read. It takes at least
16 clock cycles (Figure 9, t11) to complete conversion.
Code (decimal)
8000
7000
6000
5000
4000
3000
2000
1000
0
2044
2045
2046
2047
2048
FIGURE 5. Histogram of 8,000 Conversions of a DC Input.
FIGURE 6. Test Circuits for Timing Specifications.
FIGURE 7. Level Shift Circuit for Bipolar Input Ranges.
TRANSITION NOISE
Figure 5 shows a histogram plot for the ADS7864 following
8,000 conversions of a DC input. The DC input was set at
output code 2046. All but one of the conversions had an
output code result of 2046 (one of the conversions resulted
in an output of 2047). The histogram reveals the excellent
noise performance of the ADS7864.
BIPOLAR INPUTS
The differential inputs of the ADS7864 were designed to
accept bipolar inputs (–VREF and +VREF) around the internal
reference voltage (2.5V), which corresponds to a 0V to 5V
input range with a 2.5V reference. By using a simple op amp
circuit featuring a single amplifier and four external resis-
tors, the ADS7864 can be configured to except bipolar
inputs. The conventional
±2.5V, ±5V, and ±10V input
ranges can be interfaced to the ADS7864 using the resistor
values shown in Figure 7.
TIMING AND CONTROL
The ADS7864 uses an external clock (CLOCK, pin 22)
which controls the conversion rate of the CDAC. With an
8MHz external clock, the A/D sampling rate is 500kHz
which corresponds to a 2
µs maximum throughput time.
R
1
R
2
+IN
–IN
REF
OUT (pin 33)
2.5V
4k
20k
Bipolar Input
BIPOLAR INPUT
R
1
R
2
±10V
1k
5k
±5V
2k
10k
±2.5V
4k
20k
OPA340
ADS7864
DATA
1.4V
Test Point
3k
100pF
C
LOAD
t
R
DATA
Voltage Waveforms for DATA Rise and Fall Times t
R, and tF.
V
OH
V
OL
t
F


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn