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CLC949 Datasheet(PDF) 2 Page - National Semiconductor (TI) |
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CLC949 Datasheet(HTML) 2 Page - National Semiconductor (TI) |
2 / 12 page http://www.national.com 2 PARAMETERS CONDITIONS TYP MIN/MAX RATINGS UNITS SYMBOL Case Temperature +25˚C 0 to 70˚C -40 to 85˚C DYNAMIC CHARACTERISTICS overvoltage recovery VIN = 1.5FS 15 25 25 25 ns OR effective aperture delay 3.0 6.2 6.2 6.2 ns TA aperture jitter 7.0 15 15 15 ps(rms) AJ slew rate 400 V/ µSSR settling time 12 ns ST NOISE and DISTORTION (20MSPS) Signal-to-Noise Ratio (no harmonics) 4.985MHz; FS 68 66 66 66 dB SNR2 9.663MHz; FS 68 66 66 66 dB SNR3 Spurious-Free Dynamic Range 4.985MHz; FS -1dB 72 dBc SFDR2 9.663MHz; FS -1dB 72 63 58 55 dBc SFDR3 Intermodulation Distortion f1 = 5.58MHz @ FS -7dB; f2 = 5.70MHz @ FS -7dB -70 dBc IMD 3dB bandwidth (full power) 100 MHz BW NOISE and DISTORTION (5MSPS, low bias) Signal-to-Noise Ratio (no harmonics) 2.4MHz; FS 70 68 68 67 dB SNR1 Spurious-Free Dynamic Range 2.4MHz; FS -1dB 78 66 66 64 dBc SFDR1 NOISE and DISTORTION (25.6MSPS, high bias) Signal-to-Noise Ratio (no harmonics) 9.894MHz; FS 67 63 63 63 dB SNR4 Spurious-Free Dynamic Range 9.894MHz; FS-1dB 67 59 53 48 dBc SFDR4 DC ACCURACY and PERFORMANCE differential non-linearity dc; FS 0.5 1.0 1.0 1.0 LSB DNL integral non-linearity dc; FS 1.2 3.5 3.5 3.5 LSB INL common mode rejection ratio dc 60 dB CMRR missing codes 0 0 0 0 codes MC mid-scale offset 5.0 25 25 25 mV VIO temperature coefficient 15 µV/°C DVIO gain error 1.0 5.0 5.0 5.0 %FS GE power supply rejection Vdda dc 55 dB PSRA Vddd dc 50 dB PSRD VOLTAGE REFERENCE CHARACTERISTICS positive reference voltage (internal) 3.25 3.24-3.26 3.24-3.26 3.24-3.26 V VREFP negative reference voltage (internal) 1.25 1.24-1.26 1.24-1.26 1.24-1.26 V VREFN differential reference voltage (Vrefp - Vrefn) 2.0 1.98-2.02 1.98-2.02 1.98-2.02 V VDIFF ANALOG INPUT PERFORMANCE common mode range 2 - 3 V VCM differential range ± 2 V VDM analog input bias current ±0.1 ±1.0 ±1.0 ±1.0 µA IBN analog input capacitance 5.0 10 10 10 pF CIN DIGITAL INPUTS CMOS input voltage logic LOW 1 1 1 V VIL logic HIGH 4.0 4.0 4.0 V VIH CMOS input current logic LOW ±0.1 ±1.0 ±1.0 ±1.0 µA IIL logic HIGH ±0.1 ±1.0 ±1.0 ±1.0 µA IIH DIGITAL OUTPUTS CMOS output voltage logic LOW 0.25 0.5 0.5 0.5 V VOL logic HIGH 4.8 4.5 4.5 4.5 V VOH TIMING maximum conversion rate 30 30 30 30 MSPS CR minimum conversion rate 10 10 10 10 KSPS CRM data hold time 7.0 4.5 4.5 4.5 ns THLD pipeline delay 6.5 6.5 6.5 6.5 clocks POWER REQUIREMENTS supply current (+Vdd) 44 60 60 60 mA IDD power dissipation 20MSPS 220 300 300 300 mW PDM power dissipation (low bias) 5MSPS 65 mW PDL power dissipation (high bias) 30MSPS 400 mW PDH Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. CLC949 Electrical Characteristics (+V DD = + 5V, Medium Bias (200µA): unless specified) |
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Similar Description - CLC949 |
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