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SMH4042S-BLN Datasheet(PDF) 7 Page - Summit Microelectronics, Inc. |
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SMH4042S-BLN Datasheet(HTML) 7 Page - Summit Microelectronics, Inc. |
7 / 28 page 7 2037 8.0 8/8/00 SMH4042 PIN DESCRIPTIONS CBI_5: CBI_5 is the circuit breaker input for the supply voltage. With a series resistor placed in the supply path between the 5V early power and CBI_5, the circuit breaker will trip whenever the voltage across the resistor exceeds 50mV. DRVREN#: DRVREN# is an open-drain, active-low out- put that indicates the status of the 3 volt and 5 volt high side driver outputs (VGATE5 and VGATE3). This signal may also be used as a switching signal for the 12 volt supply. FAULT#: FAULT# is an open-drain, active-low output. It will be driven low whenever an over-current condition is detected. It will be reset at the same time that the VGATE outputs are turned back on after a reset from the host on the PWR_EN pin. 1Vref: The 1Vref output provides a 1 volt reference for pre-charging the bus signal pins. Implementing a simple unity-gain amplifier circuit will allow pre-charging a large number of pins. ISLEW: ISLEW is a Diode-connected NFET input. It may be used to adjust the 250V/s default slew rate of the high- side driver outputs VSEL: VSEL is a TTL level input used to determine which of the host power supply inputs will be monitored for valid voltage and reset generation. This is a static input and the pin should be tied to VCC or ground through a resistor. A0: Address 0 is not used by the memory array. It can be connected to ground or left floating. It must not be connected VCC. A1, A2: Address inputs 1 and 2 are used to set the two- bit device address of the memory array. The state of these inputs will determine the device address for the memory if it is on a two-wire bus with multiple memories with the same device type identifier. (For complete addressing information refer to the detailed memory operation sec- tion that follows.) SCL: The SCL input is used to clock data into and out of the memory array. In the write mode, data must remain stable while SCL is HIGH. In the read mode, data is clocked out on the falling edge of SCL. SDA: The SDA pin is a bidirectional pin used to transfer data into and out of the memory array. Data changing from one state to the other may occur only when SCL is LOW, except when generating START or STOP conditions. SDA is an open-drain output and may be wire-ORed with any number of open-drain outputs. BD_SEL1# BD_SEL2#: These are active low TTL level inputs with internal pull-ups to VCC. When pulled low they indicate full board insertion. When used in a “non-High Availability” application these inputs will be the last con- nector pins to make contact with the host backplane. On the host side, the signals should be directly tied to ground. In a “High Availability” application these inputs can be the last pins to mate with the backplane. Alternatively, they can be actively driven by the host or be connected to switches interfaced to the board ejectors or any combina- tion. Regardless, BOTH inputs MUST be low before the SMH4042 will begin to turn on the backend voltage. GND: Ground should be applied at the same time as early-power. HEALTHY#: HEALTHY# is an open-drain, active-low output indicating card side power inputs are above their reset trip levels. SGNL_VLD#: SGNL_VLD# is an open-drain, active-low output that indicates card side power is valid and the internal card side PCI_RST# timer has timed out. PWR_EN: PWR_EN is a TTL level input that allows the host to enable or disable the power to the individual card. During initial power up, this signal would start in a low state and then be driven high during software initialization. If this signal is driven low, the power supply control outputs will be driven into the inactive state, and the reset signals asserted. In a “non-High Availability” system this input can be tied high. The PWR_EN input is also used to reset the SMH4042 circuit breakers. After an over-current condition is de- tected the VGATE outputs can be turned back on by first taking PWR_EN low then returning it high. PCI_RST#: PCI_RST# is a TTL level input used as a reset input signal from the host interface. A high to low transition (held low longer than 40ns) will initiate a reset sequence. The LOCAL_PCI_RST# output and the RESET output will be driven active for a minimum period of tPURST. If the PCI_RST# input is held low longer than tPURST the reset outputs will continue to be driven until PCI_RST# is released. VSEL-Voltage Host Voltage Select Monitored Low 5 Volt or Mixed-Mode High 3.3 Volt Only |
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