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NCV7428MW3R2G Datasheet(PDF) 8 Page - ON Semiconductor

Part # NCV7428MW3R2G
Description  System Basis Chip with Integrated LIN and Voltage Regulator
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NCV7428MW3R2G Datasheet(HTML) 8 Page - ON Semiconductor

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Table 7. AC CHARACTERISTICS (VS = 5.5 V to 28 V; TJ = −40°C to +150°C; unless otherwise specified. For the transmitter
parameters, the following bus loads are considered: L1 = 1 k
W / 1 nF; L2 = 660 W / 6.8 nF; L3 = 500 W / 10 nF)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
LIN TRANSMITTER
D1
Duty Cycle 1 =
tBUS_REC(min) / (2 x tBIT)
THREC(max) = 0.744 x VS
THDOM(max) = 0.581 x VS
tBIT = 50 ms
VS = 7 V to 18 V
0.396
0.5
D2
Duty Cycle 2 =
tBUS_REC(max) / (2 x tBIT)
THREC(min) = 0.422 x VS
THDOM(min) = 0.284 x VS
tBIT = 50 ms
VS = 7.6 V to 18 V
0.5
0.581
D3
Duty Cycle 3 =
tBUS_REC(min) / (2 x tBIT)
THREC(max) = 0.778 x VS
THDOM(max) = 0.616 x VS
tBIT = 96 ms
VS = 7 V to 18 V
0.417
0.5
D4
Duty Cycle 4 =
tBUS_REC(max) / (2 x tBIT)
THREC(min) = 0.389 x VS
THDOM(min) = 0.251 x VS
tBIT = 96 ms
VS = 7.6 V to 18 V
0.5
0.590
tfallNS
LIN falling edge normal slope
Normal Mode; VS = 12 V
22.5
ms
triseNS
LIN rising edge normal slope
Normal Mode; VS = 12 V
22.5
ms
tsymNS
LIN slope symmetry normal slope
Normal Mode; VS = 12 V
−4
0
4
ms
tfallLS
LIN falling edge low slope (Note 12)
Normal Mode; VS = 12 V
45
ms
triseLS
LIN rising edge low slope (Note 12)
Normal Mode; VS = 12 V
45
ms
ttx_prop_down
Propagation Delay of TxD to LIN.
TxD high to low
(Note 11)
10
ms
ttx_prop_up
Propagation Delay of TxD to LIN.
TxD low to high
(Note 11)
10
ms
tTxD_timeout
TxD dominant timeout
TxD = Low; LIN dominant
timeout enabled
7
13
24
ms
LIN RECEIVER
trec_prop_down
Propagation delay of receiver falling
edge
0.1
6
ms
trec_prop_up
Propagation delay of receiver rising
edge
0.1
6
ms
trec_sym
Propagation delay symmetry
Trec_prop_down
Trec_prop_up
−2
2
ms
tLIN_wake
Dominant duration for wakeup
LIN in wakeup mode
30
80
150
ms
MODE TRANSITIONS AND TIMEOUTS
tsynch
Input signal synchronization delay
5
15
40
ms
tsynch_action
Delay from the asynchronous input
pin change to the system state
change
11
25
55
ms
tmodsel_set
Low power mode selection delay
17
30
55
ms
treset
RSTN pulse extension
2
5
10
ms
tVOUT_RES_filt
Undervoltage detection filter time
11
25
55
ms
11. Values based on design and characterization. Not tested in production.
12. For low slope versions only (NV7428L5 and NV7428L3)


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