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SDA3302 Datasheet(PDF) 3 Page - Siemens Semiconductor Group |
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SDA3302 Datasheet(HTML) 3 Page - Siemens Semiconductor Group |
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3 / 27 page  Semiconductor Group 3 Circuit Description (cont’d) P0-P2 The software-switched outputs (P0, P1, P2) can be used for direct band selection (20-mA current output). P4-P7 P4, P5, P6 and P7 are open-collector outputs for a variety of different purposes. The test bit T1 = 1 switches the test signals f REF (4 MHz/512) and Cy (divided input signal) to P6 and P7. CAS Four different chip addresses can be set by appropriate connection of pin CAS. I2C-Bus Interface SCL, SDA Data are exchanged between the processor and the PLL on the I2C bus. The clock is produced by the processor (input SCL), while pin SDA works as an input or output depending on the direction of the data (open collector; external pullup resistor). Both inputs have hysteresis and a lowpass characteristic, which enhances the noise immunity of the I2C bus. The data from the processor are applied to an I2C bus controller and filed in registers according to their function. When the bus is free, both lines are in the marking state (SDA, SCL are high). Each telegram begins with a start condition and ends with the stop condition. Start condition: SDA goes low while SCL remains high; stop condition: SDA goes high while SCL remains high. All further data exchanges occur while SCL is low and are accepted by the controller with the positive clock edge. For what follows, refer to the table of logic allocations. All telegrams are transmitted byte by byte, followed by a ninth clock pulse, during which the controller puts the SDA line on low (acknowledge condition). The first byte consists of seven address bits, with which the processor selects the PLL from a number of peripheral devices (chip select). The eighth bit is always low. In the data portion of the telegram the first bit of the first or third data byte determines whether a divider ratio or control information follows. In each case the byte following the first byte must be of the same data type (or a stop condition). V S, GND When the supply voltage is applied, a power-on reset circuit prevents the PLL from putting the SDA line on low, which would block the bus. SDA 3302 Family |
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