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SA1110 Datasheet(PDF) 67 Page - Intel Corporation |
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SA1110 Datasheet(HTML) 67 Page - Intel Corporation |
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67 / 406 page  SA-1110 Developer’s Manual 8-1 Clocks 8 This section describes the Intel ® StrongARM* SA-1110 Microprocessor (SA-1110) clocks. The following diagram shows the distribution of clocks in the SA-1110. The 3.6864-MHz oscillator feeds both PLLs. The primary PLL provides clocks for the core logic and a 7.36-MHz clock for several of the serial controllers. The core, Dcaches, and read and write buffers use either the full-speed core clock or the divided-down clock. The LCD controller, DMA, memory controller, and GPIO use the core clock divided by 2 (RCLK). The 32.768-kHz oscillator feeds the real-time clock (RTC) and the power manager logic. The secondary PLL provides the clock for the UDC, the ICP, and the MCP. The oscillators and PLLs are completely integrated with the SA-1110 and require no external devices other than the crystals for operation.The following figure shows a block diagram of the clocking system for the SA-1110. Figure 8-1. SA-1110 Clock System Block Diagram * Other brands and names are the property of their respective owners. A8054-01 32.768 kHz Oscillator Primary PLL 59 MHz - 200 MHz Secondary PLL 48 MHz GPIO 27 Peripherals UART: 7.36 MHz ICP: 7.36 or 48 MHz MCP/SSP: 7.36 or 12 MHz PPC: 7.36 MHz UDC: 48 MHz 3.6864 MHz Oscillator Divide by 2 Intel® ARM* SA-1 Core LCD Controller RTC and Power Manager DMA Controller Memory Controller I/O Controller Write Buffer I-Cache D-Cache Read Buffer |
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