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S3C2510A Datasheet(PDF) 4 Page - Samsung semiconductor

Part No. S3C2510A
Description  16/32-bit RISC micro-controller is a cost-effective, high-performance micro-controller solution for Ethernet-based systems, for example
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Maker  SAMSUNG [Samsung semiconductor]
Homepage  http://www.samsung.com/Products/Semiconductor
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S3C2510A Datasheet(HTML) 4 Page - Samsung semiconductor

 
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PRODUCT OVERVIEW
S3C2510A
1-4
ARM940T
The ARM940T cached processor is a member of the ARM9 Thumb family of high-performance 32-bit system-on-
a-chip processor solutions. It provides a complete high performance CPU subsystem, including ARM9TDMI RISC
integer CPU, 4KB instruction/data caches, write buffer, and protection unit, with an AMBA bus interface. The
ARM9TDMI core within the ARM940T executes both the 32-bit ARM and 16-bit Thumb instruction sets, allowing
the user to trade off between high performance and high code density. It is binary compatible with ARM7TDMI,
ARM10TDMI, and StrongARM processors, and is supported by a wide range of tools, operating systems, and
application software.
Memory organization
Memory system is composed of 8 ROM/SRAM/Flash/Ext I/O banks and 2 SDRAM banks. Each ROM bank is fixed
with 16M-byte address range and is supported with multiplexed and non-multiplexed address/data bus capability.
Each SDRAM bank is supported with 128 MByte.
Two Ethernet Controllers
The S3C2510A includes two Ethernet controllers, which enables the user to configure SOHO router, internet
gateway, etc. The main features are as follows.
— Buffered DMA (BDMA) engine using burst mode
— BDMA Tx/Rx buffers (256-byte/256-byte)
— MAC Tx/Rx FIFOs (80-byte/16-byte) to support re-transmit after collision without DMA request
— Data alignment logic
— Support for old and new media (compatible with existing 10M-bit/s networks)
— 10/100 Mbps operation to increase price/performance options and to support phased conversions
— Full IEEE 802.3 compatibility for existing applications
— Media Independent interface (MII) or 7-wire interface
— Station management (STA) signaling for external physical layer configuration and link negotiation
— On-chip CAM (21 addresses)
— Full-duplex mode for doubled bandwidth
— Pause operation hardware support for full-duplex flow control
— Long packet mode for specialized environments
— Short packet mode for fast testing
— PAD generation for ease of processing and reduced processing time


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