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4X16E83VTW-6 Datasheet(PDF) 6 Page - List of Unclassifed Manufacturers

Part # 4X16E83VTW-6
Description  4 MEG x 16 EDO DRAM
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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4X16E83VTW-6 Datasheet(HTML) 6 Page - List of Unclassifed Manufacturers

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two methods to disable the outputs and keep them
disabled during the CAS# HIGH time. The first method
is to have OE# HIGH when CAS# transitions HIGH and
keep OE# HIGH for tOEHC thereafter. This will disable
the DQs, and they will remain disabled (regardless of
the state of OE# after that point) until CAS# falls again.
The second method is to have OE# LOW when CAS#
transitions HIGH and then bring OE# HIGH for a
minimum of tOEP anytime during the CAS# HIGH
period. This will disable the DQs, and they will remain
disabled (regardless of the state of OE# after that point)
until CAS# falls again (see Figure 3). During other
cycles, the outputs are disabled at tOFF time after RAS#
and CAS# are HIGH or at tWHZ after WE# transitions
LOW. The tOFF time is referenced from the rising edge
of RAS# or CAS#, whichever occurs last. WE# can also
perform the function of disabling the output drivers
under certain conditions, as shown in Figure 4.
EDO-PAGE-MODE operations are always initiated
with a row address strobed in by the RAS# signal,
followed by a column address strobed in by CAS#, just
like for single location accesses. However, subsequent
column locations within the row may then be accessed
at the page mode cycle time. This is accomplished by
cycling CAS# while holding RAS# LOW and entering
new column addresses with each CAS# cycle. Returning
RAS# HIGH terminates the EDO-PAGE-MODE
operation.
DRAM REFRESH
The supply voltage must be maintained at the speci-
fied levels, and the refresh requirements must be met in
order to retain stored data in the DRAM. The refresh
requirements are met by refreshing all rows in the
4 Meg x 16 DRAM array at least once every 64ms (8,192
rows for 8 or 4,096 rows for 8). The recommended
procedure is to execute 4,096 CBR REFRESH cycles,
either uniformly spaced or grouped in bursts, every
64ms. The MEM4X16E43VTW refreshes one row for every
CBR cycle. For either device, executing 4,096 CBR
cycles will refresh the entire device. The CBR REFRESH
will invoke the internal refresh counter for automatic
RAS# addressing. Alternatively, RAS#-ONLY REFRESH
capability is inherently provided. However, with this
method, only one row is refreshed on each cycle. JEDEC
strongly recommends the use of CBR REFRESH for this
device.
The self refresh mode is also available.
The self refresh feature is initiated by
performing a CBR Refresh cycle and holding RAS# low
for the specified tRASS. The self refresh mode allows
the user the choice of a fully static, low-power data
retention mode or a dynamic refresh mode at the extended
refresh period of 128ms, or 31.25µs per cycle, when
using a distributed CBR refresh. This refresh rate can be
applied during normal operation, as well as during a
standby or battery backup mode.
The self refresh mode is terminated by driving RAS#
HIGH for a minimum time of t RPS. This delay allows for
the completion of any internal refresh cycles that may
be in process at the time of the RAS# LOW-to-HIGH
transition. If the DRAM controller uses a distributed
CBR refresh sequence, a burst refresh is not required
upon exiting self refresh, however, if the controller is
using RAS# only or burst CBR refresh then a burst
refresh using t RC (MIN) is required.
EDO PAGE MODE (continued)
4 MEG x 16
EDO DRAM


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