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HT83C51DC Datasheet(PDF) 5 Page - Honeywell Solid State Electronics Center |
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HT83C51DC Datasheet(HTML) 5 Page - Honeywell Solid State Electronics Center |
5 / 12 page 5 HT83C51 The Programmable Counter Array (PCA) contains a single 16-bit counter/timer made up of the CL and CH registers. This timer is used by all 5 capture/compare modules. Its clock input can be programmed to be from one of four sources. These are the oscillator frequency divided by 12, the oscillator frequency divided by 4, Timer 0 overflow, and an external clock input, ECI, on the alternate function of port pin P1.2. The serial port has physically separate receive and transmit buffers, automatic address recognition and four modes of operation as shown below. Mode Description Baud Rate 0 8-bit shift register 1/12 times oscillator freq. 1 8-bit UART variable 2 9-bit UART 1/64 or 1/32 times oscillator freq. 3 9-bit UART variable There are seven interrupt sources in the HT51. Two are external interrupts (INT0n, INT1n), three are timer interrupts (Timer 0, Timer 1, and Timer2), one is a PCA interrupt, and one is a serial port interrupt as shown below. PCA interrupt enable Timer 2 interrupt enable Serial port interrupt enable Timer 1 interrupt enable External interrupt 1 enable Timer 0 interrupt enable External interrupt 0 enable The reset input is the RST pin. A reset is accomplished by holding the RST pin high for a minimum of 4 clock periods while the clock is running. The CPU generates an internal reset from the external signal. The port pins are driven to the reset state 2 oscillator periods after a valid 1 is detected on the RST pin. While RST is high, PSENn is pulled high, ALE is pulled low, and the port pins are pulled weakly high. All SFRs are reset to their reset values. The internal Data Memory content is not affected by reset. In addition, if the HT51 is in Idle or Power Down mode prior to activation of RST, the HT51 will be taken out of Idle or Power Down mode by the reset. The processor will begin operation on the second machine cycle after the RST line is brought low. A memory access PCA COUNTER /TIMER will be made immediately after the RST line is brought low, but the data is not brought into the processor. The memory access will be repeated on the next machine cycle and actual processing will begin at that time. The instruction set for the HT51 is compatible to the Intel MCS-51 instruction set used on the 8XC51FC. SERIAL PORT INTERRUPTS RESET INSTRUCTION SET AC CHARACTERISTICS The AC characteristics for the HT51 are shown in the following tables. Each of the timing symbols has 5 charac- ters. The first character is always a ‘T’ (Time). The other characters, depending on their positions, stand for the logical name of a signal or the logical status of that signal. The following is a list of the characters and what they stand for: A: Address Q: OutputData C: Clock R: RDn signal D: Data T: Time H: Logic level HIGH V: Valid I: Instruction W: WRn signal (program memory contents) X: No longer a L: Logic level LOW, or ALE valid logic level P: PSENn Z: Float For example, TAVLL = Time from address valid to ALE low. The characteristics given are over the operating conditions T A = -55°C to +225°C, VDD = 5V ± 10 %, VSS = 0V. The load capacitance on Port 0, ALE and PSENn = 100 pF. Load capacitance for all other outputs = 50 pF. Inputs during AC testing are to be driven at V DD - 0.5V for logic 1 and 0.45 V for logic 0. Timing measurements are to be made at V IH min for logic 1 and VIL max for logic 0. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs, and begins to float when a 100 mV change from the loaded V OL/VOH level occurs. Timing diagrams are shown to illustrate the signal relationships depicted in the tables. |
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