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CY7C185 Datasheet(PDF) 4 Page - Cypress Semiconductor

Part # CY7C185
Description  8K x 8 Static RAM
Download  11 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C185 Datasheet(HTML) 4 Page - Cypress Semiconductor

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CY7C185
Document #: 38-05043 Rev. *A
Page 4 of 11
Switching Characteristics Over the Operating Range[6]
7C185-15
7C185-20
7C185-25
7C185-35
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
15
20
25
35
ns
tAA
Address to Data Valid
15
20
25
35
ns
tOHA
Data Hold from Address Change
3
5
5
5
ns
tACE1
CE1 LOW to Data Valid
15
20
25
35
ns
tACE2
CE2 HIGH to Data Valid
15
20
25
35
ns
tDOE
OE LOW to Data Valid
8
9
12
15
ns
tLZOE
OE LOW to Low Z
3
3
3
3
ns
tHZOE
OE HIGH to High Z[7]
7
8
10
10
ns
tLZCE1
CE1 LOW to Low Z
[8]
3
5
5
5
ns
tLZCE2
CE2 HIGH to Low Z
3
3
3
3
ns
tHZCE
CE1 HIGH to High Z
[7, 8]
CE2 LOW to High Z
7
8
10
10
ns
tPU
CE1 LOW to Power-Up
CE2 to HIGH to Power-Up
0
0
0
0
ns
tPD
CE1 HIGH to Power-Down
CE2 LOW to Power-Down
15
20
20
20
ns
Write Cycle[9]
tWC
Write Cycle Time
15
20
25
35
ns
tSCE1
CE1 LOW to Write End
12
15
20
20
ns
tSCE2
CE2 HIGH to Write End
12
15
20
20
ns
tAW
Address Set-up to Write End
12
15
20
25
ns
tHA
Address Hold from Write End
0
0
0
0
ns
tSA
Address Set-up to Write Start
0
0
0
0
ns
tPWE
WE Pulse Width
12
15
15
20
ns
tSD
Data Set-up to Write End
8
10
10
12
ns
tHD
Data Hold from Write End
0
0
0
0
ns
tHZWE
WE LOW to High Z[7]
7
7
7
8
ns
tLZWE
WE HIGH to Low Z
3
5
5
5
ns
Notes:
6.
Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
7.
tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.
8.
At any given temperature and voltage condition, tHZCE is less than tLZCE1 and tLZCE2 for any given device.
9.
The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. All 3 signals must be active to initiate a write and either
signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.


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