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S6E1C12D0AGV20000 Datasheet(PDF) 1 Page - Cypress Semiconductor |
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S6E1C12D0AGV20000 Datasheet(HTML) 1 Page - Cypress Semiconductor |
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1 / 100 page  S6E1C1 Series 32-bit ARM® Cortex®-M0+ FM0+ Microcontroller Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 002-00234 Rev.*B Revised March 4, 2016 The S6E1C1 Series is a series of highly integrated 32-bit microcontrollers designed for embedded controllers aiming at low power consumption and low cost. This series has the ARM Cortex-M0+ Processor with on-chip Flash memory and SRAM, and consists of peripheral functions such as various timers, ADC and communication interfaces (UART, CSIO (SPI), I2C, I2S, and Smart Card). The products which are described in this data sheet are placed into TYPE3-M0+ product categories in "FM0+ Family Peripheral Manual". Features 32-bit ARM Cortex-M0+ Core Processor version: r0p1 Maximum operating frequency: 40.8 MHz Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 24 peripheral interrupt with 4 selectable interrupt priority levels 24-bit System timer (Sys Tick): System timer for OS task management Bit Band Operation Compatible with Cortex-M3 bit band operation. On-Chip Memory Flash memory Up to 128 Kbytes Read cycle: 0 wait-cycle Security function for code protection SRAM The on-chip SRAM of this series has one independent SRAM . Up to 16 Kbytes 4Kbytes: can retain value in Deep standby Mode Multi-Function Serial Interface (Max 6channels) 3 channels with 64Byte FIFO (Ch.4, 6 and 7), 3 channels without FIFO (Ch.0, 1 and 3) The operation mode of each channel can be selected from one of the following. UART CSIO (CSIO is known to many customers as SPI) I2C UART Full duplex double buffer Parity can be enabled or disabled. Built-in dedicated baud rate generator External clock available as a serial clock Hardware Flow control* : Automatically control the transmission by CTS/RTS (only ch.4) * : S6E1C12B0A/S6E1C11B0A and S6E1C12C0A/S6E1C11C0A do not support Hardware Flow control. Various error detection functions (parity errors, framing errors, and overrun errors) CSIO (also known as SPI) Full duplex double buffer Built-in dedicated baud rate generator Overrun error detection function Serial chip select function (ch1 and ch6 only) Data length: 5 to 16 bits I2C Standard-mode (Max: 100 kbps) supported / Fast-mode (Max 400 kbps) supported. I2S (MFS-I2S) Using CSIO (Max 2 ch: ch.4, ch.6) and I2S clock generator Supports two transfer protocol • I2S • MSB-justified Master mode only I2C Slave I2C Slave supports the slave function of I2C and wake-up function from Standby mode. Descriptor System Data Transfer Controller (DSTC) (64 Channels) The DSTC can transfer data at high-speed without going via the CPU. The DSTC adopts the Descriptor system and, following the specified contents of the Descriptor that has already been constructed on the memory, can access directly the memory / peripheral device and performs the data transfer operation. It supports the software activation, the hardware activation, and the chain activation functions A/D Converter (Max: 8 Channels) 12-bit A/D Converter Successive approximation type Conversion time: 2.0 μs @ 2.7 V to 3.6 V Priority conversion available (2 levels of priority) Scan conversion mode Built-in FIFO for conversion data storage (for scan conversion: 16 steps, for priority conversion: 4 steps) Base Timer (Max: 8 Channels) The operation mode of each channel can be selected from one of the following. |
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