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S6E1A11C0AGV2 Datasheet(PDF) 1 Page - Cypress Semiconductor |
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S6E1A11C0AGV2 Datasheet(HTML) 1 Page - Cypress Semiconductor |
1 / 95 page S6E1A11B0A/C0A S6E1A12B0A/C0A 32-Bit ARM ® Cortex® FM0+ based Microcontroller Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 002-05091 Rev.*A Revised February 10, 2016 The S6E1A1 Series is a series of highly integrated 32-bit microcontrollers designed for embedded controllers aiming at low power consumption and low cost. This series has the ARM Cortex-M0+ Processor with on-chip Flash memory and SRAM, and consists of peripheral functions such as various timers, ADCs and communication interfaces (UART, CSIO, I2C, LIN). The products which are described in this data sheet are placed into TYPE1-M0+ product categories in "FM0+ Family PERIPHERAL MANUAL". Features 32-bit ARM Cortex-M0+ Core Processor version: r0p1 Maximum operating frequency: 40 MHz Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 32 peripheral interrupt with 4 selectable interrupt priority levels 24-bit System timer (Sys Tick): System timer for OS task management Bit Band operation Compatible with Cortex-M3 bit band operation On-Chip Memories Flash memory Up to 88 Kbyte Read cycle:0 wait-cycle Security function for code protection SRAM The on-chip SRAM of this series has one independent SRAM. SRAM: 6 Kbyte Multi-function Serial Interface (Max 3channels) 128 bytes with FIFO in all channels (The number of FIFO steps varies depending on the settings of the communication mode or bit length.) The operation mode of each channel can be selected from one of the following. UART CSIO LIN I 2C UART Full duplex double buffer Parity can be enabled or disabled. Built-in dedicated baud rate generator External clock available as a serial clock Various error detection functions (parity errors, framing errors, and overrun errors) CSIO Full duplex double buffer Built-in dedicated baud rate generator Overrun error detection function Serial chip select function (ch.1 and ch.3 only) Data length: 5 to 16 bits LIN LIN protocol Rev.2.1 supported Full duplex double buffer Master/Slave mode supported LIN break field generation function (The length is variable between 13 bits and 16 bits.) LIN break delimiter generation function (The length is variable between 1 bit and 4 bits.) Various error detection functions available (parity errors, framing errors, and overrun errors) I2C Standard-mode (Max: 100 kbps) supported / Fast-mode (Max 400kbps) supported. DMA Controller (2 channels) The DMA Controller has its own bus independent of the CPU, and CPU and DMA Controller can process simultaneously. 2 independently configurable and operable channels It can start a transfer with a software request or a request from a built-in peripheral. Transfer address area: 32 bits (4 Gbyte) Transfer mode: block transfer/burst transfer/demand transfer Transfer data type: byte/halfword/word Transfer block count: 1 to 16 Number of transfers: 1 to 65536 |
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