CBC34803 EnerChip™ RTC

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DS-72-34 V.20

Page 10 of 18

Preliminary

Registers With Special Programming Considerations

The following registers have special operations that require programmer attention when using the CBC34803

parts. Listed below are these registers by category of issue:

Key Register Access Values

The following registers require a write to the Configuration Key register of a specific value to allow a one-time

access. The Configuration Key register is automatically reset after the register is written:

Oscillator Control [0x1C] -> Write Configuration Key register to A1 hex (0xA1) prior to access

Trickle [0x20]

-> Write Configuration Key register to 9D hex (0x9D) prior to access

BREF Control [0x21]

-> Write Configuration Key register to 9D hex (0x9D) prior to access

AFCTRL [0x26]

-> Write Configuration Key register to 9D hex (0x9D) prior to access

BATMODE I/O [0x27]

-> Write Configuration Key register to 9D hex (0x9D) prior to access

OCTRL [0x30]

-> Write Configuration Key register to 9D hex (0x9D) prior to access

Timing Register Holdoff During Read or Write

Reading any of the following registers in an autoincrement address or burst mode must finish the burst

in 10 milliseconds to avoid losing time. This is because the timing chain freezes until the burst is done to

avoid nonsensical time reads and can only assure correct time if you finish the entire register burst in 10

milliseconds. Reading the timing registers (Hundredths ->Years) takes about 100 clocks so a 10KHz bus clock

should be able to read the registers in the required 10mS if you don’t delay between reads.

These registers are Hundredths, Seconds, Minutes, Hours (24 Hour), Hours (12 Hour), Date, Months and Years.

Status Register

The Status register [0x0F] was listed as read-only in earlier documentation but all bits can be read or written

unless the ARST bit of the Control 1 [0x10] register is set which will cause a reset of interrupt bits (TIM, BL,

ALM, WDT, XT1, XT2) on any Status read.

Relationships Between Control1 Register and Oscillator Control Register

The Stop bit in the Control1 [0x10] register invalidates the OMODE bit in the Oscillator Status [0x1D] register.

The LKO2 bit in the Oscillator Status register locks out the R/W functionality of the OUTB bit of the Control1

register.

THE FOLLOWING REGISTER BIT SETTINGS ARE IMPORTANT FOR PROPER OPERATION

OSC.Control [0x1C, bit 4]:

The default value of AOS out of reset is 0. THIS MUST TO BE REPROGRAMMED TO

1. To enable low power RC Oscillator to RUN while in the backup power state to increase run time.

BREF [0x21, bits 7:4]:

The default value of BREF out of reset is 1111. Do not change the contents of this

register. This sets the VDD-to-backup battery switchover voltage threshold.

BATMODE I/O [0x27, bit 7]:

The default value of IOBM out of reset is 1. THIS MUST TO BE REPROGRAMMED

TO 0. Setting this bit to 0 disables the bus interface in the backup power state to reduce currents through the

bus I/Os.

Cal_XT [0x14], Cal_RC_Hi [0x15], and Cal_RC_Low [0x16]:

must be programed with values that provide

the desired clock accuracy. A description of the calibration process follows in this datasheet. Also refer to

Applications Note AN-1058 for register value administration details.