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CLC451AJ Datasheet(PDF) 10 Page - National Semiconductor (TI) |
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CLC451AJ Datasheet(HTML) 10 Page - National Semiconductor (TI) |
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10 / 12 page  http://www.national.com 10 Figure 11: Power Derating Curve Layout Considerations A proper printed circuit layout is essential for achieving high frequency performance. Comlinear provides evaluation boards for the CLC451 (CLC730013-DIP, CLC730027-SOIC, CLC730068-SOT) and suggests their use as a guide for high frequency layout and as an aid for device testing and characterization. General layout and supply bypassing play major roles in high frequency performance. Follow the steps below as a basis for high frequency layout: s Include 6.8 µF tantalum and 0.1µF ceramic capacitors on both supplies. s Place the 6.8 µF capacitors within 0.75 inches of the power pins. s Place the 0.1 µF capacitors less than 0.1 inches from the power pins. s Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance. s Minimize all trace lengths to reduce series inductances. s Use flush-mount printed circuit board pins for prototyping, never use high profile DIP sockets. Evaluation Board Information Data sheets are available for the CLC730013/ CLC730027 and CLC730068 evaluation boards. The evaluation board data sheets provide: s Evaluation board schematics s Evaluation board layouts s General information about the boards The CLC730013/CLC730027 data sheet also contains tables of recommended components to evaluate several of Comlinear’s high speed amplifiers. This table for the CLC451 is illustrated below. Refer to the evaluation board data sheet for schematics and further information. Components Needed to Evaluate the CLC451 on the Evaluation Board: s Rin, Rout - Typically 50Ω (Refer to the Basic Operation section of the evaluation board data sheet for details) s Rt - Optional resistor for inverting gain configura- tions (Select Rt to yield desired input impedance = Rg || Rt) s C1, C2 - 0.1µF ceramic capacitors s C3, C4 - 6.8µF tantalum capacitors Components not used: s C5, C6, C7, C8 s R1 thru R8 The evaluation boards are designed to accommodate dual supplies. The boards can be modified to provide single supply operation. For best performance; 1) do not connect the unused supply, 2) ground the unused supply pin. Special Evaluation Board Considerations for the CLC451 To optimize off-isolation of the CLC451, cut the Rf trace on both the CLC730013 and the CLC730027 evaluation boards. This cut minimizes capacitive feedthrough between the input and the output. Figure 12 shows where to cut both evaluation boards for improved off-isolation. Figure 12: Evaluation Board Changes SPICE Models SPICE models provide a means to evaluate amplifier designs. Free SPICE models are available for Comlinear’s monolithic amplifiers that: s Support Berkeley SPICE 2G and its many derivatives s Reproduce typical DC, AC, Transient, and Noise performance s Support room temperature simulations The readme file that accompanies the diskette lists released models, and provides a list of modeled parame- ters. The application note OA-18, Simulation SPICE Models for Comlinear’s Op Amps, contains schematics and a reproduction of the readme file. Single Supply Cable Driver The typical application shown on the front page shows the CLC451 driving 10m of 75 Ω coaxial cable. The CLC451 is set for a gain of +2V/V to compensate for the divide-by-two voltage drop at Vo. Application Circuits 730013 REV C Cut trace here R8 R5 OUT C6 C2 C1 C5 C8 IN RF C7 -Vcc +Vcc GND Comlinear A National Semiconductor Company (303) 226-0500 + + Cut trace here Ambient Temperature ( °C) 0 0.2 0.4 0.6 0.8 1.0 -40 -20 0 20 40 60 80 100 120 180 AJP AJE SOT 140 160 |
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