Electronic Components Datasheet Search |
|
PYB20-Q48-S3-DIN Datasheet(PDF) 6 Page - CUI INC |
|
PYB20-Q48-S3-DIN Datasheet(HTML) 6 Page - CUI INC |
6 / 7 page cui.com CUI Inc │ SERIES: PYB20-DIN │ DESCRIPTION: DC-DC CONVERTER date 06/16/2015 │ page 6 of 7 1. Recommended circuit This series has been tested according to the following recommended testing circuit before leaving the factory. This series should be tested under load (see Figure 2). If you want to further decrease the input/output ripple, you can increase the capacitance accord- ingly or choose capacitors with low ESR (see Table 2). However, the capacitance of the output filter capacitor must be appropriate. If the capacitance is too high, a startup problem might arise. For every channel of the output, to ensure safe and reliable operation, the maximum capacitance must be less than the maximum capacitive load (see Table 3). 2. Output voltage trimming Leave open if not used. Application Circuit for Trim pin Formula for Trim Resistor (part in broken line is the interior of models) Note: Value for R1, R2, R3, and Vref refer to Table 4 R T: Trim Resistor a: User-defined parameter, no actual meanings Vo': The trim up/down voltage APPLICATION NOTES Figure 2 Figure 3 Table 2 Table 3 Table 4 Single Vout (Vdc) Cin (µF) Cout (µF) Dual Vout (Vdc) Cin (µF) Cout1 (µF) 3.3 100 470 -- -- -- 5 100 470 ±5 100 220 12 100 220 ±12 100 100 15 100 220 ±15 100 100 24 100 100 -- -- -- Vout (Vdc) R1 (kΩ) R2 (kΩ) R3 (kΩ) Vref (V) 3.3 4.801 2.863 15 1.24 5 2.883 2.864 10 2.5 12 10.971 2.864 17.8 2.5 15 14.497 2.864 17.8 2.5 24 24.872 2.863 20 2.5 Note: 1. Minimum load shouldn't be less than 5%, otherwise ripple may increase dramatically. Operation under minimum load will not damage the converter, however, they may not meet all specifications listed. 2. Maximum capacitive load is tested at input voltage range and full load. 3. All specifications are measured at Ta=25°C, humidity<75%, nominal input voltage and rated output load unless otherwise specified. +Vo 0V R2 R1 R3 Vref RT Trim 0V R2 R1 R3 Vref RT Trim +Vo Trim up Trim down DC DC Vin GND +Vo 0V Cin Cout Vin GND +Vo 0V Cin Cout DC DC -Vo Cout Dual Output Single Output a -a R 2 a R 1 R2 -a R1 -R3 -R3 : a= Vref Vref Vo’ - Vref Vo’ - Vref R1 R= T : a= R2 R= T up down Note: 1. For each output. Note: 1. For each output. Single Vout (Vdc) Max. Capacitive Load (μF) Dual Vout (Vdc) Max. Capacitive Load1 (μF) 3.3 10200 -- -- 5 4020 5 4800 12 1035 12 800 15 705 15 500 24 470 -- -- For more information, please visit the product page. |
Similar Part No. - PYB20-Q48-S3-DIN |
|
Similar Description - PYB20-Q48-S3-DIN |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |