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CLC407 Datasheet(PDF) 6 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. CLC407
Description  Low-Cost, Low-Power Programmable Gain Buffer with Disable
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
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CLC407 Datasheet(HTML) 6 Page - National Semiconductor (TI)

   
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Use
power-supply
bypassing
capacitors
when
operating this amplifier. Choose quality 0.1
µF ceramics
for C1 and C2. Choose quality 6.8µF tantalum capacitors
for C3 and C4. Place the 0.1µF capacitors within 0.1
inches from the power pins. Place the 6.8
µF capacitors
within 3/4 inches from the power pins.
Special Evaluation Board
Considerations for the CLC407
To optimize off-isolation of the CLC407, cut the Rf trace on
both the 730013 and the 730027 evaluation boards. This
cut minimizes capacitive feedthrough between the input
and the output. Figure 4 shows where to cut both evalu-
ation boards for improved off-isolation.
Figure 4
Video Performance vs. IEX
Improve the video performance of the CLC407 by drawing
extra current from the amplifier’s output stage. Using a
single external resistor as shown in Figure 5, you can
adjust the differential phase. Video performance vs. IEX is
illustrated below in Graph 2.
This graph represents
positive video performance with negative synchronization
pulses.
Graph 2
The value for Rpd in Figure 5 is determined by:
at +5V supplies.
Figure 5
Video Cable Driver
The CLC407 was designed to produce exceptional video
performance at all three closed-loop gains. At the non-
inverting gain of 2V/V configuration, back terminate the
cable using Rout. A typical cable driving configuration is
shown below in Figure 6.
Figure 6
N:1 Mux Cable Driver
The CLC407 is capable of multiplexing several signals on a
single analog output bus. The front page shows how a 2:1
multiplexer is implemented. An N:1 multiplexer is implement-
ed in an analogous fashion by using an N:1 decoder to
enable/disable the appropriate number of CLC407’s.
Ordering Information
Model
Temperature Range
Description
CLC407AJP
-40˚C to +85˚C
8-pin PDIP
CLC407AJE
-40˚C to +85˚C
8-pin SOIC
CLC407AIB
-40˚C to +85˚C
8-pin CerDIP
CLC407ALC
-40˚C to +85˚C
dice
CLC407A8B
-55˚C to +125˚C
8-pin CerDIP, MIL-STD-883
CLC407AMC
-55˚C to +125˚C
dice, MIL-STD-883
Contact factory for other packages and DESC SMD number.
Package Thermal Resistance
Package
qjc
qjA
Plastic (AJP)
75˚/W
125˚/W
Surface Mount (AJE)
130˚/W
150˚/W
CerDip
65˚/W
155˚/W
730013
REV C
Cut trace here
SMA
Output
SMA
Input
Rin
50
Rout
50
+5V
-5V
+
+
C1
0.1
µfd
C2
0.1
µfd
C3
6.8
µfd
C4
6.8
µfd
J1 = 0
1
CLC407
7
6
8
5
3
4
2
Rpd
IEX
Differential Gain & Phase vs. IEX
IEX in mA
405 G
h1
0.25
0.20
0.15
0.10
0.05
0
2
0
4
6
8
10
0.25
0.20
0.15
0.10
0.05
0
Phase
Gain
12
14
16
18
R
5
I
pd
EX
=
Coax
50
SMA
Input
Rin
50
Rout
50
+5V
-5V
+
+
C1
0.1
µfd
C2
0.1
µfd
C3
6.8
µfd
C4
6.8
µfd
J1 = 0
1
CLC407
7
6
8
5
3
4
2
50
Video
Output
R8
R5
OUT
C6
C2
C1
C5
C8
IN
RF
C7
-Vcc
+Vcc
GND
Comlinear
A National Semiconductor Company
(303) 226-0500
+
+
407 Fig 3 (Right)
Cut trace here
http://www.national.com
6


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