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CLC407 Datasheet(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. CLC407
Description  Low-Cost, Low-Power Programmable Gain Buffer with Disable
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
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CLC407 Datasheet(HTML) 4 Page - National Semiconductor (TI)

   
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Closed Loop Gain Selection
The CLC407 is a current feedback op amp with
Rf = Rg = 250Ω on chip (in the package). Select from
three closed loop gains without using any external gain or
feedback resistors.
Implement gains of +2, +1, and
-1V/V by connecting pins 2 and 3 as described in the
chart below.
The gain accuracy of the CLC407 is excellent and
stable over temperature change.
The internal gain
setting resistors, Rf and Rg are diffused silicon resistors
with a process variation of ± 20% and a temperature
coefficient of ˜ 2000ppm/°C. Although their absolute
values change with processing and temperature, their
ratio (Rf/Rg) remains constant. If an external resistor is
used in series with Rg, gain accuracy over temperature
will suffer .
Non-Inverting Unity Gain Considerations (Av = +1V/V)
Achieve a gain of +1V/V by removing all resistive and
capacitive connections between pin 2 and ground plane.
Any capacitive coupling between pin 2 and ground will
cause high frequency peaking in the frequency domain
response and overshoot in the time domain response.
Minimize this capacitive coupling during layout by removing
ground plane near pins 1, 2, and 3. This minimization
should produce a response similar to the plot labeled
“open” in Graph 1. If desired flatness is greater than plot
“open” in Graph 1, two options remain to further flatten
the frequency response. First, try shorting the inverting
input (pin 2) to the non-inverting input (pin 3).
This
response is labeled “short” in Graph 1.
Next, try
inserting a 300
Ω resistor R between the non-inverting
input (pin 2) as shown in Figure 1.
This response is
labeled “300
Ω ” in Graph 1. Notice an “open” produces a
response with obvious peaking and maximum bandwidth,
a “short” minimizes peaking and bandwidth, and finally
300
Ω slightly extends bandwidth with minimal peaking.
Graph 1
Gain
Input Connections
Acl
Non-Inverting (pin3)
Inverting (pin2)
-1V/V
ground
input signal
+1V/V
input signal
NC (open)
+2V/V
input signal
ground
CLC407 Typical Performance Characteristics (A
V = +2, Rf = 250Ω: Vcc = + 5V, RL = 100Ω unless specified)
IBI, IBN, VIO vs. Temperature
-60
-20
140
Temperature (oC)
VIO
4.0
3.0
2.0
1.0
0
-1.0
1.0
0
-1.0
-2.0
-3.0
-4.0
20
60
100
IBI
IBN
CLC407 OPERATION
Small Signal Pulse Response
Time (5ns/div)
0.20
0.10
-0.10
-0.20
0.00
AV-1
AV+2
Large Signal Pulse Response
Time (5ns/div)
2.0
1.0
-1.0
-2.0
0.0
AV-1
AV+2
Settling Time vs. Capacitive Load
10
100
1000
CL (pF)
CL
1k
Rs
+
-
250
250
V
o = 2V step
Ts
Rs
CLC407
50
40
30
20
10
0
100
80
60
40
20
0
Short Term Settling Time
Time (ns)
0.2
0.1
-0.1
-0.2
0.0
020
100
80
60
40
Vout = 2Vstep
PSRR and CMRR
10k
100k
1M
Frequency (Hz)
10M
100M
60
50
40
30
20
10
PSRR
CMRR
Frequency Response vs.
Unity Gain Configuration
Frequency (MHz)
1
10
100
Short
300
Open
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