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CY27C256-70WC Datasheet(PDF) 1 Page - Cypress Semiconductor

Part # CY27C256-70WC
Description  32K x 8-Bit CMOS EPROM
Download  11 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY27C256-70WC Datasheet(HTML) 1 Page - Cypress Semiconductor

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32K x 8-Bit CMOS EPROM
fax id: 3013
CY27C256
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
May 1993 – Revised August 1994
1CY 27C2 56
Features
• Wide speed range
— 45 ns to 200 ns (commercial and military)
• Low power
— 248 mW (commercial)
— 303 mW (military)
• Low standby power
— Less than 83 mW when deselected
±10% Power supply tolerance
Functional Description
The CY27C256 is a high-performance 32,768-word by 8-bit
CMOS EPROM. When disabled (CE HIGH), the CY27C256
automatically powers down into a low-power stand-by mode.
The CY27C256 is packaged in the industry standard 600-mil
DIP, PLCC, and TSOP packages. The CY27C256 is also avail-
able in a CerDIP package equipped with an erasure window
to provide for reprogrammability. When exposed to UV light,
the EPROM is erased and can be reprogrammed. The mem-
ory cells utilize proven EPROM floating gate technology and
byte-wide intelligent programming algorithms.
The CY27C256 offers the advantage of lower power and su-
perior performance and programming yield. The EPROM cell
requires only 12.5V for the super voltage, and low current re-
quirements allow for gang programming. The EPROM cells
allow each memory location to be tested 100% because each
location is written into, erased, and repeatedly exercised prior
to encapsulation. Each EPROM is also tested for AC perfor-
mance to guarantee that after customer programming, the
product will meet both DC and AC specification limits.
Reading the CY27C256 is accomplished by placing active
LOW signals on OE and CE. The contents of the memory location
addressed by the address lines (A0 - A14) will become available on
the output lines (O0 - O7).
Note:
1.
For PLCC only: Pins 1 and 17 are common and tied to the die attach pad. They must therefore be DU (don’t use) for the PLCC package.
Logic Block Diagram
Pin Configurations
27c256–1
A12
A11
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
POWER–DOWN
O7
O6
O5
O4
O3
O2
O1
O0
CE
256 x 1024
PROGRAMABLE
ARRAY
8 x 1 OF 128
MULTIPLEXER
A10
A13
A14
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
24
23
22
21
13
14
25
28
27
26
12
31
4
5
6
7
8
9
10
32 1
30
13
14151617
26
25
24
23
22
21
11
181920
27
28
29
32
15
A12
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
VCC
A13
A8
A9
O7
O6
O4
O5
O3
27c256–2
27c256–3
A9
A11
O7
O6
A8
VPP
A14
27C256
A11
OE
A10
CE
NC
A5
A4
A3
A2
A6
A1
O0
A0
NC
OE
A10
CE
DIP/Flatpack
27C256
ROW
LCC/PLCC[1]
OE
ADDRESS
COLUMN
ADDRESS
ADDRESS
DECODER


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