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IDT71016 Datasheet(PDF) 6 Page - Integrated Device Technology

Part No. IDT71016
Description  CMOS Static RAM 1 Meg (64K x 16-Bit)
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT71016 Datasheet(HTML) 6 Page - Integrated Device Technology

   
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6.42
6
IDT71016, CMOS Static RAM
1 Meg (64K x 16-bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 2(1)
NOTES:
1. A write occurs during the overlap of a LOW
CS, LOW BHE or BLE, and a LOW WE.
2.
OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and
data to be placed on the bus for the required tDW. If
OE is HIGH during a WE controlled write cycle, this requirement does not apply and the
minimum write pulse is as short as the specified tWP.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the
CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4)
NOTES:
1.
WE is HIGH for Read Cycle.
2. Address must be valid prior to or coincident with the later of
CS, BHE, or BLE transition LOW; otherwise tAA is the limiting parameter.
3. Transition is measured ±200mV from steady state.
ADDRESS
DATAOUT
3210 drw 07
(3)
(3)
(3)
DATA
VALID
tAA
tRC
tOE
tOLZ
tCHZ
tOHZ
OUT
(3)
tACS
(3)
tBLZ
tCLZ
(2)
tBE
tOH
tBHZ
(3)
(2)
,
OE
CS
BHE, BLE
ADDRESS
CS
DATAIN
3210 drw 08
(5)
(5)
(5)
DATAIN VALID
tWC
tAS
tWHZ
(2)
tCW
tCHZ
tOW
tWR
WE
tAW
DATAOUT
tDW
tDH
PREVIOUS DATA VALID
DATA VALID
BHE , BLE
tBW
tWP
(5)
tBHZ
(3)
,


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