4

04-02-051B

I/O with

independent

output enable

I/O

Q D

Input with optional

register/latch

A

B

C

D

1

2

OE

DQ

08-14-008A

Figure 8. LCC & IOC With Two Outputs

Global Cells

The global cells, shown in Figure 9, are used to direct

global clock signals and/or control terms to the LCCs and

IOCs. The global cells allow a clock to be selected from the

CLK1 pin, CLK2 pin, or a product term from the logic array

(PCLK). They also provide polarity control for IOC clocks

enabling

rising

or

falling

clock

edges

for

input

registers/latches. Note that each individual LCC clock has

its own polarity control. The global cell includes sum-of-

products control terms for global reset and preset, and a

fast product term control for LCC register-type, used to

save product terms for loadable counters and state

machines (see Figure 10). The PA7540 provides two

global cells that divides the LCC and IOCs into two groups,

A and B. Half of the LCCs and IOCs use global cell A, half

use global cell B. This means, for instance, two high-speed

global clocks can be used among the LCCs.

Global Cell: LCC & IOC

MUX

MUX

CLK1

CLK2

PCLK

Reg-Type

Preset

Reset

LCC Resets

LCC Presets

LCC Reg-Type

IOC Clocks

LCC Clocks

Group A & B

08-14-009A

Figure 9. Global Cells

R e g ister T yp e C h ang e F eatu re

G lobal Cell can dynamically change user-

selected LCC registers from D to T or from D

to JK. This saves product terms for loadable

counters or state machines. Use as D register

to load, use as T or JK to count. Timing allows

dynamic operation.

T

R

P

Q

D

R

P

Q

Reg-T ype from Global Cell

E x am p le:

Product terms for 10 bit loadable binary counter

D uses 57 product terms (47 count, 10 load)

T uses 30 product terms (10 count, 20 load)

D/T uses 20 product terms (10 count, 10 load)

08-14-010A

Figure 10. Register Type Change Feature

PEEL™ Array Development Support

Development support for PEEL™ Arrays is provided by

Anachip and manufacturers of popular development tools.

Anachip offers the powerful WinPLACE Development

Software (free to qualified PLD designers).

The PLACE software includes an architectural editor, logic

compiler, waveform simulator, documentation utility and a

programmer interface. The PLACE editor graphically

illustrates and controls the PEEL™ Array’s architecture,

making the overall design easy to understand, while

allowing the effectiveness of boolean logic equations, state

machine design and truth table entry. The PLACE compiler

performs logic transformation and reduction, making it

possible to specify equations in almost any fashion and fit

the most logic possible in every design. PLACE also

provides a multi-level logic simulator allowing external and

internal signals to be simulated and analyzed via a

waveform display.(See Figures 10a-c)

PEEL™ Array development is also supported by popular

development tools, such as ABEL via Anachip’s PEEL™

Array fitters. A special smart translator utility adds the

capability to directly convert JEDEC files for other devices

into equivalent JEDEC files for pin-compatible PEEL™

Arrays.

Programming

PEEL™ Arrays are EE-reprogrammable in all package

types, plastic-DIP, PLCC and SOIC. This makes them an

ideal development vehicle for the lab. EE -

reprogrammability is also useful for production, allowing

unexpected changes to be made quickly and without