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CLC030 Datasheet(PDF) 20 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. CLC030
Description  SMPTE 292M/259M Digital Video Serializer with Video and Ancilliary Data FIFOs and Integrated Cable Driver
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
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CLC030 Datasheet(HTML) 20 Page - National Semiconductor (TI)

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Device Operation (Continued)
TABLE 4. Video Raster Format Parameters
Format
Code
[4,3,2,1,0]
Format
Specification
Frame
Rate
Lines
Active Lines
Samples
Active
Samples
00001
SDTV, 54
SMPTE 344M
60I
525
507/487
3432
2880
00010
SDTV, 36
SMPTE 267M
60I
525
507/487
2288
1920
00011
SDTV, 27
SMPTE 125M
60I
525
507/487
1716
1440
01001
SDTV, 54
ITU-R BT 601.5
50I
625
577
3456
2880
01010
SDTV, 36
ITU-R BT 601.5
50I
625
577
2304
1920
01011
SDTV, 27
ITU-R BT 601.5
50I
625
577
1728
1440
10001
HDTV, 74.25
SMPTE 260M
30I
1125
1035
2200
1920
10010
HDTV, 74.25
SMPTE 274M
30I
1125
1080
2200
1920
10011
HDTV, 74.25
SMPTE 274M
30P
1125
1080
2200
1920
11001
HDTV, 74.25
SMPTE 274M
25I
1125
1080
2640
1920
11010
HDTV, 74.25
SMPTE 274M
25P
1125
1080
2640
1920
11100
HDTV, 74.25
SMPTE 295M
25I
1250
1080
2376
1920
11101
HDTV, 74.25
SMPTE 274M
24P
1125
1080
2750
1920
10100
HDTV, 74.25
SMPTE 296M
60P
750
720
1650
1280
The HD Only bit when set to a logic-1 locks the CLC030 into
the high definition data range and frequency. In systems
designed to handle only high definition signals, enabling HD
Only reduces the time required for the CLC030 to establish
frequency lock and determine the HD format being pro-
cessed.
The SD Only bit when set to a logic-1 locks the CLC030 into
the standard definition data ranges and frequencies. In sys-
tems designed to handle only standard definition signals,
enabling SD Only reduces the time required for the CLC030
to establish frequency lock and determine the format being
processed. When SD Only and HD Only are set to logic-0,
the device operates in SD/HD mode.
The H, V, and F bits of the FORMAT 1 register correspond to
input TRS data bits 6, 7 and 8, respectively. The meaning
and function of this data is the same for both standard
definition (SMPTE 125M) and high definition (SMPTE 292M
luminance and colour difference) video data. Polarity is
logic-1 equals HIGH-true. These bits are registered for the
duration of the applicable field.
TEST 0 REGISTER (Address 0Dh)
The Test Pattern Select bits determine which test pattern is
output when the Test Pattern Generator (TPG) mode or the
Built-in Self-Test (BIST) mode is enabled.
Table 5 gives the
codes corresponding to the various test patterns. All HD
colour bars test patterns are BIST data. Standard Definition
BIST test patterns are: NTSC, 27MHz, 4x3 Colour Bars and
PAL, 27MHz, 4x3 PLL Pathological.
The TPG Enable bit when set to a logic-1 enables the Test
Pattern Generator function and built-in self-test (BIST). This
bit is mapped to I/O port bit 7 in the default condition. Note
that the input pulldown on the I/O port bit has the effect of
overriding the logic level of data being written into the regis-
ter via the Ancilliary/Control Data Port. In cases where it is
desired to control the state of TPG Enable through the
control register instead of the multi-function I/O port, bit 7 of
the multi-function I/O port must be remapped to another bit in
the control registers. Remapping to a read-only function is
recommended to avoid possible conflicting data being writ-
ten into the remapped location.
The Pass/Fail bit indicates the result of running the built-in
self-test. This bit is a logic-1 for a pass condition. The bit is
mapped to I/O port bit 6 in the default condition.
VIDEO INFO 0 REGISTER (Address 0Eh)
The NSP (New Sync Position) bit indicates that a new or
out-of-place TRS character has been detected in the input
data. This bit is set to a logic-1 and remains set for at least
one horizontal line period or unless re-activated by a subse-
quent new or out-of-place TRS. It is reset by an EAV TRS
character.
The EAV (end of active video) and SAV (start of active video)
bits track the occurrence of the corresponding TRS charac-
ters.
Lock Detect is registered as a control signal and is a logic-1
when the PLL is locked and a valid format has been de-
tected. This bit may be programmed as an output on the
multi-function I/O port. This bit is mapped to I/O port bit 4 in
the default condition. This function also includes logic to
check the stability of the device after the digital logic reset is
released following PLL lock. If the system is not fully stable,
the logic is automatically reset. LOCK DETECT also com-
bines the function of indicating that the CLC030 has de-
tected the video format being received. This format detect
function involves determination of the major raster param-
eters such as line length, number of video lines in a frame,
and so forth. This is done so that information like line num-
bering can be correctly inserted. The PLL itself will have
locked in about 50 microseconds (HD rates, 150 microsec-
onds for SD) or less; however, resolution of all raster param-
eters may take the majority of a frame.
The VPG Filter Enable bit when set enables operation of the
Video Pattern Generator filter. Operation of this filter causes
the insertion of transition codes in the chroma and luma data
of colour bar test patterns where these patterns change from
one bar to the next. This filter reduces the magnitude of
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