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CLC030 Datasheet(PDF) 11 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. CLC030
Description  SMPTE 292M/259M Digital Video Serializer with Video and Ancilliary Data FIFOs and Integrated Cable Driver
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com

CLC030 Datasheet(HTML) 11 Page - National Semiconductor (TI)

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Device Operation (Continued)
Ancilliary Data Functions
The CLC030 can insert Ancilliary Data into the serial data
stream. This ancilliary data and related control characters
are defined in the relevant SMPTE standards and may re-
side in the horizontal and vertical blanking intervals. The
data can consist of different types of message packets in-
cluding audio data. The serial ancilliary data space must be
formatted according to SMPTE 291M. The CLC030 supports
ancilliary data in the chrominance channel (C’r/C’b) only for
high-definition operation. Ancilliary data for standard defini-
tion follows the requirements of SMPTE 125M.
Figure 3 shows the sequence of clock, data and control
signals for writing ancilliary data to the port. In ancilliary data
write mode, 10-bit Ancilliary Data is written into the port
using bits AD[9:0] and routed to the ancilliary data FIFO.
From the FIFO, the ancilliary data can be written into the
ancilliary data spaces in the serial video data stream. Ancil-
liary data write mode is invoked by making the ANC/CTRL
input high and the RD/WR input low. Data presented to the
port on a falling edge of ACLK is written into the FIFO on the
next rising edge of ACLK. Ancilliary data may only be written
to the FIFO when in the ancilliary data mode. Ancilliary data
cannot be read from the port.
Admission of ancilliary data to and insertion into the video
data stream from the FIFO is controlled by a system of
masking and control bits in the control registers. The details
and functions of these control registers and bits is explained
later in this datasheet.
FIGURE 1. Control Data Read Timing (2 read and 1 write cycle shown)
FIGURE 2. Control Data Write Timing

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