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CLC030 Datasheet(PDF) 9 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. CLC030
Description  SMPTE 292M/259M Digital Video Serializer with Video and Ancilliary Data FIFOs and Integrated Cable Driver
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
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CLC030 Datasheet(HTML) 9 Page - National Semiconductor (TI)

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Timing Diagram
Device Operation
The CLC030 SDTV/HDTV Serializer is used in digital video
signal origination equipment: cameras, video tape recorders,
telecines and video test and other equipment. It converts
parallel SDTV or HDTV component digital video signals into
serial format. Logic levels within this equipment are normally
produced by LVCMOS logic devices. The encoder produces
serial digital video (SDV) signals conforming to SMPTE
259M, SMPTE 344M (proposed) or SMPTE 292M. The
CLC030 operates at parallel data rates of 27.0 MHz, 36.0
MHz, 54.0 MHz, 74.176MHz and 74.25 MHz. Corresponding
serial data rates are 270 Mbps, 360 Mbps, 540 Mbps,
1.4835Gbps and 1.485 Gbps. Segmented frame formats are
not supported.
VIDEO DATA PATH
The input data register accepts 10-bit standard definition or
20-bit high definition parallel data and associated clock sig-
nals having LVCMOS-compatible signal levels. All parallel
video data inputs, DV[19:0], have internal pull-down de-
vices. VCLK does not have an internal pull-down device.
Parallel video data may conform to any of several SMPTE
standards: 125M, 267M, 260M, 274M, 295M or 296M. Seg-
mented frame formats are not supported. For HDTV data,
the upper 10 bits of the DV input are luminance (luma)
information and the lower 10 bits are colour difference
(chrominance or chroma) information. For SDTV data, the
lower order 10 bits contain both luma and chroma informa-
tion. Output from this register feeds the video FIFO, video
format detection circuit, TRS character detector, SMPTE
scrambler, EDH/CRC generators, serializer/NRZI converter
and the device control system.
Data from the input data register passes into a 4-register
deep video FIFO prior to encoding and other processing.
The depth of this FIFO is set by a word written into the
VIDEO FIFO Depth[2:0] bits in the ANC 0 control register.
The video format detector automatically determines the
raster characteristics (video data format) of the parallel input
data and configures the CLC030 to properly handle the data.
This assures that the data will be properly formatted, that the
correct data rate is selected and that ancilliary data, line
numbers (HD) and CRC/EDH data are correctly inserted.
Indication of the standard being processed is stored in the
FORMAT[4:0] bits in the FORMAT 1 control data register.
This format data can be programmed for output on the
multi-function I/O port.
The CLC030 may be configured to operate at a single video
format by writing the appropriate FORMAT SET[4:0] control
data into the FORMAT 0 control register. Also, the CLC030
may be configured to handle only the standard-definition
data formats by setting the SD ONLY bit or only the high-
definition data formats by setting the HD ONLY bit in the
FORMAT 0 control register. When both of these bits are
reset the part automatically detects the data rate and range.
The TRS character detector processes the timing refer-
ence signals which control raster framing. The TRS detector
supplies control signals to the system controller to identify
the presence of the valid video data. The system controller
supplies necessary control signals to the EDH/CRC control
block. TRS character LSB-clipping as prescribed in ITU-R
BT.601 is used. LSB-clipping causes all TRS characters with
a value between 000h and 003h to be forced to 000h and all
TRS characters with a value between 3FCh and 3FFh to be
forced to 3FFh. Clipping is done prior to scrambling and
EDH/CRC character generation.
The CLC030 incorporates circuitry that implements the pro-
posed SMPTE recommended practice and method for LSB
dithering. Control of this circuitry is via the Dither Enable bit
in the VIDEO INFO 0 control register. Dithering can be
selectively enabled during the vertical blanking interval by
use of the V Dither Enable bit in the VIDEO INFO 0 control
register. The initial condition of Dither Enable and V Dither
Enable is OFF.
The SMPTE scrambler accepts 10-bit standard definition or
20-bit high definition parallel video data and encodes it using
the polynomial X9 +X4 + 1 as specified in the respective
standard in SMPTE 259M, SMPTE 344M (proposed) or
SMPTE 292M. The data is then serialized and sent to the
NRZ-to-NRZI converter before being output. The transmis-
sion bit order is LSB-first.
The NRZ-to-NRZI converter accepts NRZ serial data from
the SMPTE scrambler. The data is converted to NRZI format
using the polynomial (X + 1). The converter’s output goes to
the output cable driver amplifier.
ANCILLIARY/CONTROL DATA PATH
The Ancilliary and Control Data Port serves two functions
in the CLC030. It is used to selectively load ancilliary data
into the Ancilliary Data FIFO for insertion into the video data
stream. The utilization and flow of ancilliary data within the
device is managed by a system of control bits, masks and
IDs in the control data registers. This port also provides
read/write access to contents of the configuration and con-
trol registers. Configuration of the multi-function I/O Port is
also controlled by information stored in the control data
registers. Ancilliary and control data are input via the 10-bit
Ancilliary/Control Data Port, AD[9:0]. The signals RD/WR,
ANC/CTRL and ACLK control data flow through the port.
The operation and frequency of ACLK is completely inde-
DS200003-8
www.national.com
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