Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF HTML

CLC012 Datasheet(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. CLC012
Description  Adaptive Cable Equalizer for ITU-T G.703 Data Recovery
Download  18 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
Logo 

CLC012 Datasheet(HTML) 4 Page - National Semiconductor (TI)

 
Zoom Inzoom in Zoom Outzoom out
 4 / 18 page
background image
Electrical Characteristics (Continued)
(V
CC
= +5V, V
EE = 0V, signal source swing = 0.8 Vpp(Note 4), CAEC = 100 pF)
Parameter
Conditions
Typ
+25˚C
Min/Max
+25˚C
Min/Max
−40˚C to
+85˚C
Units
Input and Output Parameters
MUTE current input-HIGH
V
IH = 5V (Note 3)
5.0
±100
±500
nA
MUTE current input-LOW
V
IL = 0V (Note 3)
0.2
±100
±500
nA
TIMING PERFORMANCE
LOS Response Time
carrier applied
(Note 8)
150
1000
1000
ns
carrier removed
(Note 9)
150
1000
1000
ns
MUTE response time
(Note 10)
2.0
_
_
ns
MISCELLANEOUS PERFORMANCE
input resistance
single-ended
7.3
_
_
k
input capacitance
single-ended (Note 11)
1.0
_
_
pF
input return loss @ 270 MHz
Z
o =75Ω (Note 12)
19
_
_
dB
maximum cable attenuation
200 MHz (Note 13)
40
_
_
dB
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined
from tested parameters.
Note 3: J-level: spec. is 100% tested at +25˚C.
Note 4: These specifications assume an 800 mVpp signal at the cable input. Levels above and below 800 mV are allowable, but performance may vary. The cable
will attenuate the signal prior to entering the equalizer.
Note 5: Peak-to-peak jitter is defined as 6 times the rms jitter.
Note 6: For more information, see “CLC012 Operation” and “Design Guidelines”.
Note 7: 50% eye opening.
Note 8: Time from application of a valid signal to when the LOS output asserts high.
Note 9: Time from the removal of a valid signal to when the LOS output asserts low.
Note 10: Time from assertion of MUTE to when the output responds.
Note 11: Device only. Does not include typical pc board parasitics.
Note 12: Includes typical pc board parasitics.
Note 13: This sets the maximum cable length for the equalizer.
Note 14: Human body model, 1.5 k
Ω in series with 100 pF; based on limited test data.
Note 15: To maintain specified performance, do not reduce DO/DO below this level.
www.national.com
4


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn