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SKY67012-396LF Datasheet(PDF) 1 Page - Skyworks Solutions Inc. |
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SKY67012-396LF Datasheet(HTML) 1 Page - Skyworks Solutions Inc. |
1 / 15 page Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 201645D • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • April 6, 2015 1 DATA SHEET SKY67012-396LF: 300 to 600 MHz Low-Noise, Low-Current Amplifier Applications ISM, CDMA, TETRA, RFID, mobile broadcast, automobile-to- home control systems, Medical Micro-Power Networks General purpose LNAs Features Low NF: 0.85 dB @ 450 MHz Gain: 16.5 dB @ 450 MHz Flexible supply voltage from 1.8 to 5.0 V Adjustable supply current for higher IIP3 Incorporates on-die stability structures Miniature DFN (8-pin, 2 x 2 mm) package (MSL1 @ 260 C per JEDEC J-STD-020) Skyworks GreenTM products are compliant with all applicable legislation and are halogen-free. For additional information, refer to Skyworks Definition of GreenTM, document number SQ04–0074. 4 3 2 1 5 6 7 8 N/C N/C RF_IN VBIAS N/C N/C RF_OUT/VDD N/C S2396 Figure 2. SKY67012-396LF Pinout – 8-Pin DFN (Top View) RF_IN VBIAS RF_OUT/VDD Active Bias Stability Network S2395 Figure 1. SKY67012-396LF Block Diagram Description The SKY67012-396LF is a GaAs, pHEMT low-noise amplifier (LNA) with an integrated active bias. The advanced GaAs pHEMT enhancement mode process provides excellent return loss, low noise, and high linearity. The device offers the ability to externally adjust the supply current. The supply voltage is applied to the RF-OUT/VDD pin through an RF choke inductor. The VBIAS pin should be connected to the RF_OUT/VDD pin through an external resistor to control the supply current. Both RF_OUT/VDD and RF_IN pins should be DC blocked to ensure proper operation. The SKY67012-396LF is manufactured in a compact, 2 x 2 mm, 8-pin Dual Flat No-Lead (DFN) package. A functional block diagram is shown in Figure 1. The pin configuration and package are shown in Figure 2. Signal pin assignments and functional pin descriptions are provided in Table 1. |
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