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EVAL-ADM1278EBZ Datasheet(PDF) 43 Page - Analog Devices |
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EVAL-ADM1278EBZ Datasheet(HTML) 43 Page - Analog Devices |
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43 / 61 page  Data Sheet ADM1278 Rev. A | Page 43 of 61 Multiple Devices on Bus When there are several devices on the bus, the processor issues an SMBus alert response address (ARA) command to find out which device asserted the SMBAlert line. The processor reads the status bytes from that device and issues a CLEAR_FAULTS command. SMBUS ALERT RESPONSE ADDRESS The SMBus ARA is a special address that can be used by the bus host to locate any devices that need to communicate with the bus host. A host typically uses a hardware interrupt pin to monitor the SMBus alert pins of multiple devices. When the host interrupt occurs, the host issues a message on the bus using the SMBus receive byte or receive byte with PEC protocol. The special address used by the host is 0x0C. Any devices that have an SMB alert signal return their own 7-bit address as the seven MSBs of the data byte. The LSB value is not used and can be either 1 or 0. The host reads the device address from the received data byte and proceeds to handle the alert condition. More than one device may have an active SMBAlert signal and attempt to communicate with the host. In this case, the device with the lowest address dominates the bus and succeeds in transmitting its address to the host. The device that succeeds disables its SMBus alert signal. If the host sees that the SMBus alert signal is still low, it continues to read addresses until all devices that need to communicate have successfully transmitted their addresses. EXAMPLE USE OF SMBUS ARA The full sequence of steps that occurs when an SMBAlert is generated and cleared is as follows: 1. A fault or warning is enabled using the ALERT2_CONFIG command, and the corresponding status bit for the fault or warning changes from 0 to 1, indicating that the fault or warning has just become active. 2. The GPO2/ALERT2 pin becomes active (set low) to signal that an SMBAlert is active. 3. The host processor issues an SMBus ARA command to determine which device has an active alert. 4. If there are no other active alerts from devices with lower I2C addresses, this device makes the GPO2/ALERT2 pin inactive (set high) during the no acknowledge bit period after it sends its address to the host processor. 5. If the GPO2/ALERT2 pin stays low, the host processor must continue to issue SMBus ARA commands to devices to determine the addresses of all devices that require a status check. 6. The ADM1278 continues to operate with the GPO2/ALERT2 pin inactive and the contents of the status bytes unchanged until the host reads the status bytes and clears them, or until a new fault occurs. That is, if a status bit for a fault/warning that is enabled on the GPO2/ALERT2 pin and that was not already active (equal to 1) changes from 0 to 1, a new alert is generated, causing the GPO2/ALERT2 pin to become active again. DIGITAL COMPARATOR MODE The GPO1/ALERT1/CONV and GPO2/ALERT2 pins can be configured to indicate if a user defined threshold for voltage, current, or power is being exceeded. In this mode, the output pin is live and is not latched when a warning threshold is exceeded. In effect, the pin acts as a digital comparator, where the threshold is set using the warning limit threshold commands. The ALERTx_CONFIG command is used, as for the SMBAlert configuration, to select the specific warning threshold to be monitored. The GPO1/ALERT1/CONV or GPO2/ALERT2 pin then indicates if the measured value is above or below the threshold. TYPICAL APPLICATION CIRCUITS GATE Q1 MO+ HS+ HS– TIMER TIMER ADM1278-1 MO– RSENSE 4.5V TO 20V VCC VCP VCAP ISENSE UV OV 1.0V 1.0V TEMP VOUT PWGIN 1.0V VOUT 12-BIT ADC SCL SDA ADR2 ISENSE HS+ TEMP LDO CHARGE PUMP TIMEOUT IOUT GPO1/ALERT2 ENABLE GPO2/ALERT1/CONV VCBOS ISTART ISET PSET TIMEOUT CURRENT- LIMIT CONTROL REF SELECT 1.0V HS– FAULT RETRY PWRGD ADR1 CSOUT GATE DRIVE/ LOGIC LOGIC AND PMBus ANALOG VOUT ×50 + + + – – – + – GND PGND Figure 71. ADM1278-1 Typical Application Circuit |
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