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ADM1270 Datasheet(PDF) 19 Page - Analog Devices
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ADM1270 Datasheet(HTML) 19 Page - Analog Devices
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Rev. A | Page 19 of 21
GATE AND RPFG CLAMPS
The circuits driving the GATE and RPFG pins are clamped to less
than 14 V below the VCC/SENSE+ pin. These clamps ensure that
the maximum V
rating of the external FETs is not exceeded.
The reverse protection FET gate pin (RPFG) drives the gate of
an external PMOSFET. This PMOSFET, Q2, provides reverse
polarity protection to the ADM1270 and the system being
powered. If the VCC and GND pins have been reverse
connected (that is, where power is actually applied to GND),
VCC is negative with respect to the system ground. In this
condition, Q2 prevents current from flowing in the reverse
direction because the gate of Q2 is held at GND, and Q2 is off.
is not pulled below GND, and the system is protected
against a reverse polarity connection.
In the typical case where power is applied to VCC, the gate is
still pulled down and allows the FET Q2 to turn on and conduct
current in the forward direction. Operating Q2 in this way
provides a low on-resistance, low voltage drop compared to a
diode for reverse polarity protection, giving the system higher
efficiency and more headroom for operation. Figure 33 shows
the connection of Q2 and RPFG for proper operation.
FAST RESPONSE TO SEVERE OVERCURRENT
The ADM1270 includes a separate, high bandwidth, current
sense amplifier to detect a severe overcurrent that is indicative of
a short circuit. The fast response time allows the ADM1270 to
handle events of this type that could otherwise cause catastrophic
damage if not detected and dealt with very quickly. The fast
response circuit ensures that the ADM1270 can detect an
overcurrent event of approximately 200% of the normal current
limit and control the current within approximately 2 µs.
UNDERVOLTAGE AND OVERVOLTAGE
The ADM1270 monitors the supply voltage for UV and OV
conditions. The UV and OV pins are connected to the inputs
of the voltage comparators and compared to an internal 1 V
Figure 40 illustrates the voltage monitoring input connections.
An external resistor network divides the supply voltage for
monitoring. An undervoltage event is detected when the voltage
connected to the UV pin falls below 1 V, and the FET is turned
off using the 10 mA pull-up current. Similarly, when an overvoltage
event occurs and the voltage on the OV pin exceeds 1 V, the
FET is turned off using the 10 mA pull-up current.
4V TO 60V
Figure 40. Undervoltage and Overvoltage Supply Monitoring
The ADM1270 provides a dedicated ENABLE digital input pin.
The ENABLE pin allows the ADM1270 to remain off by using a
hardware signal, even when the voltage on the UV pin is greater
than 1.0 V, and the voltage on the OV pin is less than 1.0 V.
Although the UV pin can be used to provide a digital enable
signal, using the ENABLE pin for this purpose keeps the ability
of the UV pin free to monitor undervoltage conditions.
In addition to the conditions for the UV and OV pins, the
ADM1270 ENABLE input pin must be high for the device to
begin a power-up sequence.
A similar function can be achieved using the UV pin directly.
Alternatively, if the UV divider function is still required, the
configuration shown in Figure 41 can be used.
Figure 41. Using the UV Pin as an Enable
Diode D1 prevents the external driver pull-up resistor from
affecting the UV threshold. Select Diode D1 using the following
× D1) + (V
× EN) << 1.0 V (I
Ensure that the EN sink current does not exceed the specified
value. If the open-drain device has no pull-up, the diode is
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