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ADM1270 Datasheet(PDF) 17 Page - Analog Devices

Part No. ADM1270
Description  High Voltage Input Protection Device
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Maker  AD [Analog Devices]
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ADM1270 Datasheet(HTML) 17 Page - Analog Devices

 
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Data Sheet
ADM1270
Rev. A | Page 17 of 21
The default value is 50 mV and is achieved by connecting the
ISET pin directly to the VCAP pin. This circuit configuration
configures the device to use an internal 2 V reference, which
results in 50 mV at the sense inputs (see Figure 38).
40×
+
CURRENT
LIMIT
VCC/SENSE+
SENSE–
GATE
GND
LDO
VCAP
RSENSE
Q1
4V TO 60V
+
REF
SELECT
ISET
FLB
2V
CURRENT-
LIMIT
CONTROL
Figure 38. Fixed 50 mV Current Sense Limit
To program the sense voltage from 12.5 mV to 62.5 mV, an
external resistor divider sets the reference voltage on the ISET
pin (see Figure 39).
40×
+
CURRENT
LIMIT
VCC/SENSE+
SENSE–
GATE
GND
LDO
VCAP
RSENSE
Q1
4V TO 60V
+
REF
SELECT
ISET
FLB
2V
CURRENT-
LIMIT
CONTROL
Figure 39. Adjustable 12.5 mV to 62.5 mV Current Sense Limit
The VCAP pin has a 3.6 V internally generated voltage that can
set a voltage at the ISET pin. Assuming that VISET equals the
voltage on the ISET pin, select the resistor divider values to set
the ISET voltage as follows:
VISET = VSENSE × 40
where VSENSE is the current sense voltage limit.
The VCAP rail also can be used as the pull-up supply for setting
other pins. To guarantee that VCAP meets its accuracy
specifications, do not apply a load to the VCAP pin greater
than 100 µA.
FOLDBACK
Foldback is a method to actively reduce the current limit as the
voltage drop across the FET increases. This technique keeps the
power dissipation in the FET at a minimum during power-up,
overcurrent, or short-circuit events. It also reduces the need to
oversize the FET to accommodate worst-case conditions,
resulting in board size and cost savings.
Assuming that the supply voltage remains constant and within
tolerance, the ADM1270 detects the voltage drop across the FET
by sensing output voltage through a resistor divider. The device,
therefore, relies on the principle that the drain of the FET is at
the maximum expected supply voltage, and that the magnitude
of the output voltage is relative to that of the VDS of the FET.
Using a resistor divider from the output voltage to the FLB pin,
the relationship from VOUT, and thus VDS, to VFLB can be derived.
Design the resistor divider to result in a voltage equal to VISET/2
when VOUT falls below the desired level. This voltage must be
well below the working tolerance of the supply rail. As VOUT
continues to drop, the current-limit reference follows VFLB
because it is now the lowest voltage input to the current-limit
reference selector block, resulting in a reduction of the current
limit and, therefore, the regulated load current. To prevent the
current from decreasing to zero, a clamp activates when VFLB
reaches 200 mV. The current limit cannot drop below this level.
To ensure that the SOA characteristics of a particular FET are
not violated, the minimum current for this clamp varies from
design to design. However, the current-limit reference fixes this
clamp at 200 mV, which equals 10 mV across the sense resistor.
Therefore, the main ISET voltage can be adjusted to adjust the
clamp to the required percentage current reduction. For example,
if VISET equals 1.6 V, set the clamp at 25% of the maximum current.
TIMER
The TIMER pin handles the timing function with an external
capacitor, CTIMER. The two TIMER pin comparator thresholds
are VTIMERL (0.1 V) and VTIMERH (2.0 V). There are two timing
current sources as well: a 20 µA pull-up current and a 1 µA
pull-down current.
These current and voltage levels, in combination with the user
chosen value of CTIMER, determine the fault current-limit time
and the on-time of the hot swap retry duty cycle. The TIMER
pin capacitor value is determined using the following equation:
CTIMER = (tON × 20 µA)/VTIMERH
where:
tON is the time that the FET is allowed to spend in regulation at
the current limit.
VTIMERH is the TIMER high threshold.
The choice of FET is based on matching this time with the SOA
characteristics of the FET. Foldback can also be used to simplify
the selection.


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