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PI7VD9004ABH Datasheet(PDF) 10 Page - Pericom Semiconductor Corporation |
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PI7VD9004ABH Datasheet(HTML) 10 Page - Pericom Semiconductor Corporation |
10 / 73 page 10 PI7VD9008ABH Adaptive EQ 8-channel 960H Video Decoder www.pericom.com 12/12/14 PIXCLK_P VIN_0 FF 00 00 VIN_1 Cb10 Y10 Cr10 VIN_2 Cb20 Y20 Cr20 VIN_3 FF 00 00 PIXOUT_x FF PIXCLK_N Cb10 Cb20 FF 00 Y10 Y20 00 00 Cr10 Cr20 00 Time-multipexed Format with 108/ 144MHz Video Signal Processing The chip is capable of processing digital video signal to fulfill better detection in a noisy environment and achieve good image qual- ity for viewing as well. For video signal detection, a resilient SYNC TIP detection mechanism is implemented to locate VSYNC and HSYNC correctly in order to lock the video frame or video line. In general, the poor power adaptor or camera would introduce high frequency ripples coupling with sync tip to cause the misjudgment on the beginning of a video frame or line. The built-in video processing circuit is able to decouple the noise from sync tip to prevent from video loss. A sharpness filter is implemented to offer programmable 16 level gains to increase the high frequency and edge information of luma for better viewing on the contour of each object. Through the I2C serial interface, hue, contrast, brightness and saturation can be programmed in the configuration registers. Hue can be controlled in 256 steps from -180 degrees to +180 degrees. Saturation can be programmed in 256 grades. Brightness can be adjusted in 256 levels. Video Output Port The four CVBS analog video channels are converted into four individual digital video data streams. There are four video output ports (PIXOUT_0, PIXOUT_1, PIXOUT_2 and PIXOUT_3) in the chip and each video output port can carry several converted digital video data stream following ITU-R BT.656 compatible data format. The video data of each port is synchronous with the corresponding clock signals of PIXCLK_PO or PIXCLK_NO. The frequency of PIXCLK_*O can be operated at 1x, 2x or 4x of 27MHz (720H mode) or 36MHz (960H mode). When the clock frequency is 2x or 4x rate, the video port outputs 2-channel or 4-channel video data stream in time-multiplexed format. The clock phase of PIXCLK_POorPIXCLK_NOcanbe programmed by delay cells through writing delay value into the registers of PIXCLK_P_DEL or PIXCLK_N_DEL. Also, the clock polarity can be controlled through inverter by setting or resetting the register of PIXCLK_P_POL or PIXCLK_N_POL. The flexibility on changing clock phase or polarity facilitates the timing design for video data stream on PCB. 14-0207 |
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