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PI7VD9004ABH Datasheet(PDF) 30 Page - Pericom Semiconductor Corporation

Part No. PI7VD9004ABH
Description  Adaptive EQ 4-channel 960H Video Decoder
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Maker  PERICOM [Pericom Semiconductor Corporation]
Homepage  http://www.pericom.com
Logo PERICOM - Pericom Semiconductor Corporation

PI7VD9004ABH Datasheet(HTML) 30 Page - Pericom Semiconductor Corporation

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PI7VD9004ABH
Adaptive EQ 4-channel 960H Video Decoder
Pericom Semiconductor Corporation  
30 
www.pericom.com     
 
6.1.44 RESERVED REGISTER – OFFSET 8AH-9EH
6.1.45 PIXCLK 0 DELAY REGISTER– OFFSET 9FH(Default=00H)
BIT
FUNCTION
TYPE
DESCRIPTION
[3:0]
Control Clock Delay
Of PIXCLK_P0 Pin
RW
0h/1h/3h/7h/Fh values are effective
0h: No clock delay
1h: About 2ns more delay,
3h: About 4ns more delay,
7h: About 6ns more delay,
Fh: About 7ns more delay
[7:4]
Control Clock Delay
Of PIXCLK_N0 Pin
RW
0h/1h/3h/7h/Fh values are effective.
0h: No clock delay
1h: About 2ns more delay,
3h: About 4ns more delay,
7h: About 6ns more delay,
Fh: About 7ns more delay
6.1.46 RESERVED REGISTER – OFFSET A0H-B0H
6.1.47 CH8IDEN REGISTER – OFFSET B1H(Default=00H)
BIT
FUNCTION
TYPE
DESCRIPTION
[6:0]
Reserved
R
Reset to 00b
[7]
CH8IDEN
R/W
Video Channel ID number for 8 channels when fast switching
is enabled.
0: 4-channel ID only. Please refer to channel ID01 and ID34
registers for defining 4 channels’ ID numbers.
1: 8-channel ID. The ID for each channel is defined as follows.
CV_IN0A: {1’b0, CH0NUM[2:0]}
CV_IN1A: {1’b0, CH1NUM[2:0]}
CV_IN2A: {1’b0, CH2NUM[2:0]}
CV_IN3A: {1’b0, CH3NUM[2:0]}
CV_IN0B: {1’b1, CH0NUM[2:0]}
CV_IN1B: {1’b1, CH1NUM[2:0]}
CV_IN2B: {1’b1, CH2NUM[2:0]}
CV_IN3B: {1’b1, CH3NUM[2:0]}
6.1.48 RESERVED REGISTER – OFFSET B2H-C7H
6.1.49 GPIO_0_1 MODE REGISTER– OFFSET C8H(Default=00H)
BIT
FUNCTION
TYPE
DESCRIPTION
[2:0]
Output
Mode
For
GPIO_0Pin
RW
Select output mode for GPIO_0 pin
0: Output HSYNC
1: Output VSYNC
2: Field
3: H-active
4: VH-active
5: 27MHz clock output
6: VH-sync
7: GPP_VA1
[3]
General Purpose Value
RW
Set general purpose value in GPIO_0 pin
13-0174


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