PI7VD9004ABH
Adaptive EQ 4-channel 960H Video Decoder
Pericom Semiconductor Corporation
15
www.pericom.com
This device supports audio system clock with 256fs or 320fs mode, which is controlled by AIN5MD register. The record
output pin contains several channel inputs that can be defined by the registers at offset of 0xD2~ 0xDA describing the
number and sequence of recorded audio streams. It supports 8bit and 16bit record data width for trading off between
higher audio qualities and saving disk storage space. By controlling bit2 of register at offset 0xDB, the chip allows to select
the output record data width to be either 8-bit or 16-bit mode.
Figure 4-3 Audio Processing Block
13-0174
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