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PI7VD9004ABH Datasheet(PDF) 13 Page - Pericom Semiconductor Corporation

Part No. PI7VD9004ABH
Description  Adaptive EQ 4-channel 960H Video Decoder
Download  53 Pages
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Maker  PERICOM [Pericom Semiconductor Corporation]
Homepage  http://www.pericom.com

PI7VD9004ABH Datasheet(HTML) 13 Page - Pericom Semiconductor Corporation

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Adaptive EQ 4-channel 960H Video Decoder
Pericom Semiconductor Corporation  
In general, the poor power adaptor or camera would introduce high frequency ripples coupling with sync tip to cause the
misjudgment on the beginning of a video frame or line. The built-in video processing circuit is able to decouple the noise
from sync tip to prevent from video loss.
A sharpness filter is implemented to offer programmable 16 level gains to increase the high frequency and edge
information of luma for better viewing on the contour of each object. Through the I2C serial interface, hue, contrast,
brightness and saturation can be programmed in the configuration registers. Hue can be controlled in 256 steps from -180
degrees to +180 degrees. Saturation can be programmed in 256 grades. Brightness can be adjusted in 256 levels.
Video Output Port
The four CVBS analog video channels are converted into four individual digital video data streams. There are four video
output ports (PIXOUT_0, PIXOUT_1, PIXOUT_2 and PIXOUT_3) in the chip and each video output port can carry
several converted digital video data stream following ITU-R BT.656 compatible data format. The video data of each port is
synchronous with the corresponding clock signals of PIXCLK_PO or PIXCLK_NO. The frequency of PIXCLK_*O can be
operated at 1x, 2x or 4x of 27MHz (720H mode) or 36MHz (960H mode). When the clock frequency is 2x or 4x rate, the
video port outputs 2-channel or 4-channel video data stream in time-multiplexed format. The clock phase of
PIXCLK_POor PIXCLK_NOcan be programmed by delay cells through writing delay value into the registers of
PIXCLK_P_DEL or PIXCLK_N_DEL. Also, the clock polarity can be controlled through inverter by setting or resetting the
register of PIXCLK_P_POL or PIXCLK_N_POL. The flexibility on changing clock phase or polarity facilitates the timing
design for video data stream on PCB.
Figure 4-1Time-multiplexed format with 108/144MHz

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