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PI7VD9004ABH Datasheet(PDF) 44 Page - Pericom Semiconductor Corporation |
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PI7VD9004ABH Datasheet(HTML) 44 Page - Pericom Semiconductor Corporation |
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PI7VD9004ABH Adaptive EQ 4-channel 960H Video Decoder Pericom Semiconductor Corporation 44 www.pericom.com 1: The polarity of PIXCLK_P is inversed [7] PIXCLK_N_POL RW 0:The polarity of PIXCLK_N is not inversed 1: The polarity of PIXCLK_N is inversed 6.1.77 VIDEO/AUDIO DETECTION ENABLE REGISTER–OFFSET FCH (Default=FFH) BIT FUNCTION TYPE DESCRIPTION [7:0] AVDET_EN RW Enable the status register updated and interrupt request if the following video or audio source is detected. The mapping of video/audio input to each bit of the register is defined as below. Bit0: Video input CV_IN0. Bit1: Video input CV_IN1. Bit2: Video input CV_IN2. Bit3: Video input CV_IN3. Bit4: Audio input LINE_IN0. Bit5: Audio input LINE_IN1. Bit6: Audio input LINE_IN2. Bit7: Audio input LINE_IN3. 0: Disable status register updated and interrupt request 1: Enable status register updated and interrupt request 6.1.78 VIDEO/AUDIO DETECTION STATUS REGISTER–OFFSET FDH (Default=00H) BIT FUNCTION TYPE DESCRIPTION [7:0] AVDET_STATUS R Display the detection status of each video or audio source according to AVDET_EN, VDET_MODE and ADET_MODE. The mapping of video/audio input to each bit of the register is defined as below. The bits will be cleared once the register is read by software except VDET_MODE =3 or ADET_MODE=3. Bit0: Video input CV_IN0. Bit1: Video input CV_IN1. Bit2: Video input CV_IN2. Bit3: Video input CV_IN3. Bit4: Audio input LINE_IN0. Bit5: Audio input LINE_IN1. Bit6: Audio input LINE_IN2. Bit7: Audio input LINE_IN3. 0: Inactive. No event detected after the last access to this bit. 1: Active. An event is detected. 6.1.79 DEVICE ID_H REGISTER– OFFSET FEH(Default=00H) BIT FUNCTION TYPE DESCRIPTION [5:0] Reserved R Reset to 00h 13-0174 |
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