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CGS410 Datasheet(PDF) 8 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # CGS410
Description  Programmable Clock Generator
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

CGS410 Datasheet(HTML) 8 Page - National Semiconductor (TI)

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30 Circuit Operation (Continued)
Serial Bit 2
Reference Select
A logic low configures XTLIN and
XTLOUT for crystal mode A logic high configures for EX-
TREF On power-up this bit is low (crystal mode)
Serial Bits 3 4
Loop Filter Select LSB is loaded first Bit values are
mapped by the following
Bit 4
Bit 3
0
O
External Mode
0
1
500 kHz Reference
1
0
15 MHz Reference
1
1
5 MHz Reference
External mode selected on power-up
Serial Bit 5
Load Clock (LCLK) Disable A logic low enables LCLK A
logic high freezes the LCLK output low and disables the L
counter Note that this is different from the effects of the L
clock enable pin which is a synchronous disable and which
only disables the output (leaving the counter operational)
LCLK is enabled on power-up
Serial Bit 6
PCLK Disable A logic low enables CMOS
PCLK output A
logic high freezes CMOS
PCLK low CMOS
PCLK is en-
abled on power-up
Serial Bit 7
Differential (DIFF) Out Disable A logic low enables Differen-
tial Output A logic high causes both differential outputs to
be driven below 400 mV DlFF out is enabled on power-up
Serial Bit 8
Charge Pump Output (CPO) Select A logic low forces a
25 mA current pump A logic high forces a 75 mA current
pump There is a 25 mA current pump on power-up
Serial Bit 9
Charge Pump Output (CPO) Polarity A logic low forces a
‘‘normal’’ output response ie the charge pump sinks cur-
rent when the feedback signal (N counter output) leads the
reference signal (R counter output) A logic high forces an
inverted response CPO polarity is in normal mode on
power-up
Serial Bit 10
Charge Pump (CPO) Disable A logic low enables charge
pump activity A logic high Tri-States CPO activity CPO is
enabled on power-up
Serial Bit 11
Voltage Controlled Oscillator (VCO) Disable A logic low en-
ables VCO operation A logic high disables VCO activity
VCO is enabled on power-up
Serial Bit 12
External VCO Enable (XVCO
EN) A logic high enables the
external VCO path This bit is disabled on power-up
Serial Bit 13
Voltage Control Oscillator (VCO) Reset A logic high resets
the VCO This means that the charge pump output is
clamped to AGND to guarantee that the loop filter is dis-
charged VCO reset is high (enabled) on power-up A logic
low places the VCO in normal operating mode In order for
the PLL to lock this bit must be returned low after power-up
Serial Bits 14 15
Internal clock MUX
SEL LSB (bit 14) is loaded first This
MUX selects which clock signal is passed to the clock out-
puts Bit values are mapped by the following
Bit 15
Bit 14
0
0
XTAL2 Mode
0
1
P Counter Mode
1
0
External Clock Mode (Passthru)
1
1
Not Used
The XTAL2 mode is selected on power-up
Serial Bits 16 – 19
P counter modulus select LSB bit 16 is loaded first The P
modulus range is 1 – 16 continuous Serial bits 16 – 19 are
loaded with the desired modulus value b 1 (ie 0 – 15) P
counter divides by modulus 4 on power-up
Serial Bits 20 – 23
L counter modulus select LSB bit 20 is loaded first The L
modulus range is 1 – 16 continuous Serial bits 20 – 23 are
loaded with the desired modulus value b 1 (ie 0 – 15) L
counter divides by modulus 4 on power-up
Serial Bits 24 – 33
R counter modulus LSB (bit 24) is loaded first The R coun-
ter divides continuously by the binary value loaded Modulus
range is 1 – 1023 inclusive R is initialized at 20 on power-up
Loading R e 0 is undefined
Serial Bits 34 – 47
N counter modulus LSB (bit 34) is loaded first The N coun-
ter divides by the binary value loaded Modulus range is
2 – 16383 inclusive N is initialized at 120 on power-up Load-
ing N e 0orN e 1 is undefined
353 Power-Up Conditions
At power-up the control register bits are set to provide initial
operating conditions as follows
1 All clock outputs are active
2 The differential PCLK and CMOS
PCLK outputs func-
tion at a rate of XTAL2 The LCLK functions at a rate of
XTAL8
3 The status of the internal register reflects the following
N e 120
R e 20
P e 4 (bits 16 – 19 e 3)
L e 4 (bits 20 – 23 e 3)
4 All other programmable bits are low except VCO
RPST
which is set high
8


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